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DAC38RF80 Datasheet(PDF) 92 Page - Texas Instruments |
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DAC38RF80 Datasheet(HTML) 92 Page - Texas Instruments |
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92 / 155 page  92 DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 SLASEA3C – DECEMBER 2016 – REVISED JULY 2017 www.ti.com DAC38RF83 DAC38RF93 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated 8.5.15 JESD FIFO Control Register (address = 0x0D) [reset = 0x1300] Figure 92. JESD FIFO Control Register (JESD_FIFO) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 0 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 57. JESD_FIFO Field Descriptions Bit Field Type Reset Description 15 FIFO_ZEROS_DATA R/W 1 When asserted FIFO errors zero the data out of the JESD block. For test purposes this could be turned off to allow test patterns in the FIFO. 14:13 NOT USED R/W 000 Not Used 12 SRDS_FIFO_ALM_CLR R/W 0 Set to 1 to clear FIFO errors. Must be set to 0 for proper FIFO operation 11 Not used R/W 0 Not used 10:8 FIFO_OFFSET R/W 0000 Used to set the difference between read and write pointers in the JESD FIFO. 7:1 Reserved R/W 0 Reserved 0 SPI_TXENABLE R/W 0 When asserted the internal value of txenable = '1' 8.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF] Figure 93. Alarm Mask 1 Register (ALM_MASK1) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 58. ALM_MASK1 Field Descriptions Bit Field Type Reset Description 15:0 ALM_MASK1 R/W 0x00FF Each bit is used to mask an alarm. Assertion masks the alarm: bit 15 = mask lane7 lane errors bit 14 = mask lane6 lane errors bit 13 = mask lane5 lane errors bit 12 = mask lane4 lane errors bit 11 = mask lane3 lane errors bit 10 = mask lane2 lane errors bit 9 = mask lane1 lane errors bit 8 = mask lane0 lane errors bit 7 = mask lane7 FIFO flags bit 6 = mask lane6 FIFO flags bit 5 = mask lane5 FIFO flags bit 4 = mask lane4 FIFO flags bit 3 = mask lane3 FIFO flags bit 2 = mask lane2 FIFO flags bit 1 = mask lane1 FIFO flags bit 0 = mask lane0 FIFO flags |
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