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DAC38RF80 Datasheet(PDF) 5 Page - Texas Instruments |
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DAC38RF80 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 155 page  5 DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 www.ti.com SLASEA3C – DECEMBER 2016 – REVISED JULY 2017 DAC38RF83 DAC38RF93 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Changes from Original (December 2016) to Revision A Page • Changed Feature: Spectral Performance (on-chip PLL, DIFF) .............................................................................................. 1 • Changed text From: 1.23 GSPS complex per channel To: 1.25 GSPS complex per channel in the Description ................. 1 • Changed the Pin Configuration image .................................................................................................................................. 7 • Changed the Pin Functions table ........................................................................................................................................... 8 • Changed the Description of SYSREF+ From: "LVPECL SYSREF positive input." To: "LVPECL SYSREF positive input, self biased." in the Pin Functions - DAC38RF83, DAC38RF93, DAC38RF85 table .................................................... 9 • Changed the Pin Configuration image ................................................................................................................................ 10 • Changed the Pin Functions table ......................................................................................................................................... 11 • Added "Transformer (TCM2-452X-2+) loss not de-embedded 2.1 GHz output frequency" to the Full scale output power Test Conditions in Electrical Characteristics - DC Specifications.............................................................................. 14 • Changed Reference output current From: 100 mA To: 100 nA in the Electrical Characteristics - DC Specifications ......... 14 • Changed the POWER SUPPLY CURRENT AND CONSUMPTION section of the Electrical Characteristics - DC specifications table ............................................................................................................................................................... 14 • Updated the typical values for power consumption for all modes in Electrical Characteristics - DC Specifications table... 17 • Specified the test conditions for Electrical Characteristics - DC Specifications table .......................................................... 17 • Added max current and power consumption for operating Mode 1 and Mode 11 Electrical Characteristics - DC Specifications table............................................................................................................................................................... 17 • Changed VI(DPP) From: MIN = 100 V TYP = 800 V To: TYP = 800 mV MAX = 2000 mVin Electrical Characteristics - Digital Specifications table.................................................................................................................................................... 17 • Changed the typical values throughout the Electrical Characteristics - AC Specifications table ......................................... 20 • Changed the NSD Test Conditions in the Electrical Characteristics - AC Specifications table ........................................... 22 • Changed the AC PERFORMANCE – Modulated Signals section Test Conditions in the Electrical Characteristics - AC Specifications table......................................................................................................................................................... 22 • Changed From: LMFSHd = 841 To: LMFSHd = 84111 in the Typical Characteristics conditions statement ...................... 25 • Updated graphs in the Typical Characteristics section ........................................................................................................ 25 • Added: Transformer loss is not de-embedded in Figure 37 ................................................................................................ 31 • Added: VCO frequency to Figure 41 through Figure 44 ...................................................................................................... 31 • Changed text From: 1.25 GSPS complex per channel To: 1.23 GSPS complex per channel in the Description ............... 33 • Replaced the Functional Block Diagrams, Figure 45 through Figure 50.............................................................................. 33 • Updated the max input rate in Table 9 ................................................................................................................................ 44 • Updated value of pull up and pull down resistors in Figure 70 under CMOS Digital Inputs ................................................ 72 • Changed From: 2 x (DACFS -11) To: 2 mA x (DACFS - 11) in Equation 10 ...................................................................... 72 • Changed text From: "(PFD) and charge pump (CP) is required." To: "(PFD) is approximately 550 MHz." in the Internal PLL/VCO section ..................................................................................................................................................... 76 • Updated the startup sequence in Figure 167 .................................................................................................................... 141 • Replaced Figure 172 ......................................................................................................................................................... 145 |
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