DAC38RF80 datasheet(41/155 Pages) TI1

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DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

www.ti.com

SLASEA3C – DECEMBER 2016 – REVISED JULY 2017

DAC38RF83 DAC38RF93

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Table 3.

RATE

LINE RATE

PLL OUTPUT FREQUENCY

x Gbps

0.25x GHz

x Gbps

0.5x GHz

x Gbps

1x GHz

x Gbps

2x GHz

Table 4. SerDes PLL Modes Selection

MPY

EFFECT

0x20

0x28

0x30

0x40

0x42

8.25x

0x50

10x

0x60

12x

0x64

12.5x

0x78

15x

0x80

16x

0x84

16.5x

0xA0

20x

0xB0

22x

0xC8

25x

Other codes

Reserved

The wide range of multiply factors combined with the different rate modes means it is often possible to achieve a

given line rate from multiple different reference frequencies. The configuration which utilizes the highest

reference frequency achievable is always preferable.

The SerDes PLL VCO must be in the nominal range of 1.5625 - 3.125 GHz. It is necessary to adjust the loop

filter depending on the operating frequency of the VCO. If the PLL output frequency is below 2.17 GHz, VRANGE

in register SRDS_PLL_CFG (8.5.84) should be set high.

Performance of the integrated PLL can be optimized according to the jitter characteristics of the reference clock

by setting the appropriate loop bandwidth via field LB in register SRDS_PLL_CFG (8.5.84). The loop bandwidth

is obtained by dividing the reference frequency by BWSCALE, where the BWSCALE is a function of both LB and

PLL output frequency as shown in Table 5.

Table 5. SerDes PLL Loop Bandwidth Selection

EFFECT

BWSCALE vs PLL OUTPUT FREQUENCY

3.125 GHz

2.17 GHz

1.5625 GHz

Medium loop bandwidth

Ultra high loop bandwidth

Low loop bandwidth

High loop bandwidth

An approximate loop bandwidth of 8 – 30 MHz is suitable and recommended for most systems where the

reference clock is via low jitter clock input buffer. For systems where the reference clock is via a low jitter input

cell, but of low quality, an approximate loop bandwidth of less than 8 MHz may offer better performance. For

systems where the reference clock is cleaned via an ultra-low jitter LC-based cleaner PLL, a high loop bandwidth

up to 60 MHz is more appropriate. Note that the use of ultra-high loop bandwidth setting is not recommended for

PLL multiply factor of less than 8.

DAC38RF80 Datasheet(PDF) 41 Page - Texas Instruments

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