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DAC38RF80 Datasheet(PDF) 96 Page - Texas Instruments |
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DAC38RF80 Datasheet(HTML) 96 Page - Texas Instruments |
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96 / 155 page ![]() 96 DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 SLASEA3C – DECEMBER 2016 – REVISED JULY 2017 www.ti.com DAC38RF83 DAC38RF93 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated 8.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000] Figure 97. JESD Lane Skew Register (JESD_LN_SKEW) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x R R R R R R R R 7 6 5 4 3 2 1 0 0 0 0 1 0 0 1 0 R R R R R R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 62. JESD_LN_SKEW Field Descriptions Bit Field Type Reset Description 15:5 NOT USED R 0x0000 Not used 4:0 MEMIN_LANE_SKEW R 0b00000 Measure of the lane skew for each link only. Bits are READ_ONLY 8.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000] Figure 98. CMIX Configuration Register (CMIX) 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 x R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 0 0 0 1 0 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 63. CMIX Field Descriptions Bit Field Type Reset Description 15:12 CMIX_AB R/W 0x0 These bits turn on the different coarse mixing options. Combining the different options together can result in every possible n x Fs/8 [n=0->7]. Below is the valid programming table: cmix=(mem_fs8; mem_fs4; mem_fs2; mem_fsm4) 0000 : no mixing 0001 : -fs/4 0010 : fs/2 0100 : fs/4 1000 : fs/8 1100 : 3fs/8 1010 : 5fs/8 1110 : 7fs/8 11:4 Reserved R/W 00000000 0 Reserved 3:0 CMIX_CD R/W 0x0 These bits turn on the different coarse mixing options. Combining the different options together can result in every possible n x Fs/8 [n=0->7]. Below is the valid programming table: cmix=(mem_fs8; mem_fs4; mem_fs2; mem_fsm4) 0000 : no mixing 0001 : -fs/4 0010 : fs/2 0100 : fs/4 1000 : fs/8 1100 : 3fs/8 1010 : 5fs/8 1110 : 7fs/8 |
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