DAC38RF80 datasheet(69/155 Pages) TI1

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output

OUTSUM

SAME

ADJ

DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

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SLASEA3C – DECEMBER 2016 – REVISED JULY 2017

DAC38RF83 DAC38RF93

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The normal operating condition for the PAP block is the NORMAL state in Figure 68. However, when the PAP

block detects an error condition it sets the pap_trig signal to ‘1’ causing a state transition from NORMAL

operation to the ATTENUATE state.

In the ATTENUTATE state the data path gain is scaled from 1.0 down to 0.0 by a programmable step amount set

by fields PAPAB_GAIN_STEP in register PAP_GAIN_AB (8.5.31) and PAPCD_GAIN_STEP in register

PAP_GAIN_CD (8.5.33). This value is always positive with the decimal place located between the MSB and

MSB-1. Unity is equal to “1000000000”. Each clock cycle (16 samples) the PAP_GAIN is stepped down by

PAPAB_GAIN_STEP and PAPCD_GAIN_STEP until the gain is 0.

After PAP_GAIN is 0, the state machine moves on to the WAIT state. Here a programmable counter counts clock

cycles to allow the condition for the pap_trig to be fixed. Fields PAPAB_WAIT in register PAP_WAIT_AB (8.5.32)

and PAPCD_WAIT in register PAP_WAIT_CD (8.5.34) are used to select the number of clock cycles (samples =

16 x PAPAB_WAIT or 16 x PAPCD_WAIT) to wait before moving to the next state. Once the WAIT counter

equals zero and pap_trig=’0’, the state machine moves on to the GAIN state. If the WAIT equals 0 but pap_trig

still equals ‘1’ then the state machine stays in the WAIT state until pap_trig =’0’.

8.3.19 Gain Block

The GAIN block also has additional output gain control through fields GAINAB in register GAINAB (8.5.39) and

GAINCD in register GAINCD (8.5.40). Similar to PAP_GAIN value, the output gain is always positive with unity

when GAINAB or GAINCD = ”010000000000”.

To reduce the power, the gain block clock has been gated whenever the pap is disabled and GAINAB or

GAINCD is set to unity.

8.3.20 Output Summation

The OUTSUM block allows addition of samples from each DUC in the multi-DUC. It is also possible to add the

output samples from the adjacent multi-DUC. Field OUTSUM_SEL in register OUTSUM (8.5.22) controls the

summation for each multi-DUC. The functionality of the block can be represented by the following equation:

(7)

In order to avoid overflow, rounding operation is performed after the addition to reduce the word size back to 16-

bits. Exact number of bits rounded depends on the number of channels added. Table 39 shows the description of

round after the summation.

Table 39. OUTSUM Scaling and Rounding

# OF CHANNELS ADDED

# OF BITS ROUNDED

0, Use bits[15:0] from the result

Use bits[16:1] from the result and bit[0] used for rounding

Use bits[17:2] from the result and bits[1:0] used for rounding

Use bits[18:3] from the result and bit[2:0] used for rounding

Use bits[19:4] from the result and bit[3:0] used for rounding

8.3.21 Output Delay

The signal following output summation can be programmably delayed by 0-15 DACCLK cycles through field

OUTPUT_DELAY in register OUTSUM (8.5.20). The block takes 16 sample words (vec16) from both the A and B

paths and shifts the them to 32 sample long delay line.

8.3.22 Polarity Inversion

The signal following the output delay can be inverted by a 2’s complement conversion allowing the + and - DAC

outputs to be swapped by asserting field DAC_COMPLEMENT in register MULTIDUC_CFG1 (8.5.13).

8.3.23 Temperature Sensor

The DAC38RFxx incorporates a temperature sensor block which monitors the die temperature by measuring the

voltage across 2 transistors. The voltage is converted to an 8-bit digital word using a successive approximation

(SAR) analog to digital conversion process. The result is scaled, limited and formatted as a twos complement

value representing the temperature in degrees Celsius.

DAC38RF80 Datasheet(PDF) 69 Page - Texas Instruments

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