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DAC38RF80 Datasheet(PDF) 65 Page - Texas Instruments

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Part # DAC38RF80
Description  Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL
PDF  155 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC38RF80 Datasheet(HTML) 65 Page - Texas Instruments

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DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
www.ti.com
SLASEA3C – DECEMBER 2016 – REVISED JULY 2017
DAC38RF83 DAC38RF93
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
8.3.17.3 JESD204B Modes, Interpolation and Clock phase Programming
Table 36 lists the register field values required for each JESD204B mode, interpolation mode and clock phase.
The register field addresses are listed in Table 37.
Table 36. Register Programming for JESD and Interpolation Mode
Mode
Register Field Programming
L-M-F-S-
Hd
1 TX/2TX
Inter
p
CLOCK
PHASES
(1-0)
INTERP
(4-0)
CLKJESD_DI
V
(3-0)
CLKJESD_OU
T_DIV
(3-0)
L_M1
(4-0)
F_M1
(7-0)
M_M1
(7-0)
S_M1
(4-0)
HD
N_M1/N’_M
1
(4-0)
82121/NA
6
11
00011
0110
0011
00111
0x00
0x01
00001
1
01111
8
11
00100
0111
0100
12
11
00110
1010
0110
16
11
01000
1011
0111
42111/841
11
6
10
00011
0010
0011
00011
0x00
0x01
00000
1
01111
8
11
00100
0011
0100
10
11
00101
0101
0101
12
11
00110
0110
0110
16
11
01000
0111
0111
18
11
01001
1001
1000
24
11
01100
1010
1010
22210/442
10
8
01
00100
0001
0100
00001
0x01
0x01
00000
0
01111
12
10
00110
0010
0110
16
11
01000
0011
0111
18
11
01001
0100
1000
20
11
01010
0101
1001
24
11
01100
0110
1010
12410/244
10
16
01
01000
0001
0111
00000
0x03
0x01
00000
0
01111
24
10
00110
0110
1010
44210/882
10
8
01
00100
0001
0100
00011
0x01
0x03
00000
0
01111
12
10
00110
0010
0110
16
11
01000
0011
0111
24
11
01100
0110
1010
24410/484
10
16
01
01000
0001
0111
00001
0x03
0x03
00000
0
01111
24
10
01100
0010
1010
24310/483
10
24
11
01100
0011
1010
00001
0x02
0x03
00000
0
01011
Table 37. Register Field Addresses for JESD204B Modes, Interpolation and Clock Phase Programming
Register Field Name
Register
Register Address
Bit(s)
Hyperlink
INTERP
MULTIDUC_CFG1
0x0A
12-8
8.5.13
CLKJESD_DIV
SerDes_CLK
0x25
15-12
8.5.28
CLKJESD_OUT_DIV
11-8
L_M1
JESD_K_L
0x4C
4-0
8.5.47
F_M1
JESD_RBD_F
0x4B
7-0
8.5.46
M_M1
JESD_M_S
0x4D
15-8
8.5.48
S_M1
4-0
HD
JESD_N_HD_SCR
0x4E
6
8.5.49
N_M1
4-0
N_M1’ (NPRIME_M1)
12-8
JESD_PHASE_MODE
JESD_LN_EN
0x4A
1-0
8.5.45
All registers are paged!



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