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DAC38RF80 Datasheet(PDF) 83 Page - Texas Instruments

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Part # DAC38RF80
Description  Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL
PDF  155 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC38RF80 Datasheet(HTML) 83 Page - Texas Instruments

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83
DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
www.ti.com
SLASEA3C – DECEMBER 2016 – REVISED JULY 2017
DAC38RF83 DAC38RF93
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
8.5.2 IO Configuration Register (address = 0x01) [reset = 0x1800]
Figure 79. IO Configuration Register (IO_CONFIG)
15
14
13
12
11
10
9
8
0
0
0
1
1
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 44. IO_CONFIG Field Descriptions
Bit
Field
Type
Reset
Description
15:14
GPO0_SEL
RW
00
Selects the JESD SYNC_N signal coming out the GPO0 pin.
Both bits can be asserted which does an oring of the SYNC_N
signals from each multi-DUC.
bit 0 = 1 then multi-DUC1 SYNC_N used
bit 1 = 1 then multi-DUC2 SYNC_N is used
13:12
SYNC0B_SEL
RW
01
Selects the JESD SYNC_N signal coming out the SYNC0B pin.
Both bits can be asserted which does an oring of the SYNC_N
signals from each multi-DUC.
bit 0 = 1 then multi-DUC1 SYNC_N used
bit 1 = 1 then multi-DUC2 SYNC_N is used
11:10
SYNC1B_SEL
RW
10
Selects the JESD SYNC_N signal coming out the SYNC1B pin.
Both bits can be asserted which does an oring of the SYNC_N
signals from each multi-DUC.
bit 0 = 1 then multi-DUC1 SYNC_N used
bit 1 = 1 then multi-DUC2 SYNC_N is used
9:8
GPO1_SEL
RW
00
Selects the JESD SYNC_N signal coming out the GPO1 pin.
Both bits can be asserted which does an oring of the SYNC_N
signals from each multi-DUC.
bit 0 = 1 then multi-DUC1 SYNC_N used
bit 1 = 1 then multi-DUC2 SYNC_N is used
7
SPI4_ENA
RW
0
When set to a '1' the chip is in 4 pin SPI interface mode.
6
Reserved
RW
0
Reserved
5:0
ATEST
RW
000000
Select the analog test points:
000000: ATEST is off (ATEST Must be off during normal
operation)
000001, 010001, 000110: VSSCLK
000010: VDDPLL1
000101: VDDCLK
000111, 001010, 010000: VDDAPLL18
001011: VDDAVCO18
001101: VDDS18
001110: VDDE1
001111, 111010, 111011, 111100: DGND
010011: VDDTX1
101001, 110001: AGND
101111, 111101, 111110, 11111: VDDDIG1
110000: VDDA18



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