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DAC38RF80 Datasheet(PDF) 55 Page - Texas Instruments

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Part # DAC38RF80
Description  Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL
PDF  155 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC38RF80 Datasheet(HTML) 55 Page - Texas Instruments

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DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
www.ti.com
SLASEA3C – DECEMBER 2016 – REVISED JULY 2017
DAC38RF83 DAC38RF93
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
Table 26. ws_core Chain
FIELD
DESCRIPTION
HEAD (STARTING FROM THE MSB OF CHAIN)
RETIME
No function.
ENPLL
PLL enable.
MPY[7:0]
PLL multiply.
VRANGE
VCO range.
ENDIVCLK
Enable DIVCLK output
LB[1:0]
Loop bandwidth
RECEIVER (FOR EACH LANE 0,1,2,3)
ENRX
Receiver enable.
SLEEPRX
Receiver sleep mode.
BUSWIDTH[2:0]
Bus width.
RATE[1:0]
Operating rate.
INVPAIR
Invert polarity.
TERM[2:0]
Termination.
ALIGN[1:0]
Symbol alignment.
LOS[2:0]
Loss of signal enable.
CDR[2:0]
Clock/data recovery.
EQ[2:0]
Equalizer.
EQHLD
Equalizer hold.
ENOC
Offset compensation.
LOOPBACK[1:0]
Loopback.
BSINRXP
Boundary scan initialization.
BSINRXN
Boundary scan initialization.
RESERVED
Reserved.
Testpatt[2:0]
Test pattern selection.
TESTFAIL
Test failure (real time).
LOSTDTCT
Loss of signal detected (real time).
BSRXP
Boundary scan data.
BSRXN
Boundary scan data.
OCIP
Offset compensation in progress.
EQOVER
Receiver signal over equalized.
EQUNDER
Receiver signal under equalized.
LOSTDTCT
Loss of signal detected (sticky).
SYNC
Re-alignment done, or aligned comma output
(sticky).
RETIME
No function.
TAIL (ENDING WITH THE LSB CHAIN)
CLKBYP[1:0]
Clock bypass.
SLEEPPLL
PLL sleep mode.
RESERVED
Reserved.
LOCK
PLL lock (real time).
BSINITCLK
Boundary scan initialization clock.
ENBSTX
Enable TX boundary scan.
ENBSRX
Enable RX boundary scan.
ENBSPT
RX pulse boundary scan.
RESERVED
Reserved.
NEARLOCK
PLL near to lock.
UNLOCK
PLL lock (sticky).



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