DAC38RF80 datasheet(78/155 Pages) TI1

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rwb

D15

D14

D13

D12

D11

D10

Instruction Cycle

Data Transfer Cycle

td(Data)

SDEN\

SCLK

SDIO

SDEN\

SCLK

SDIO

SDO

D15

D14

D13

D12

D11

D10

SDO

Data n

Data n-1

rwb

D15

D14

D13

D12

D11

D10

Instruction Cycle

Data Transfer Cycle

tS(SDEN\)

tS(SDIO) tH(SDIO)

tSCLK

SDEN\

SCLK

SDIO

SDEN\

SCLK

SDIO

DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3C – DECEMBER 2016 – REVISED JULY 2017

www.ti.com

DAC38RF83 DAC38RF93

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Figure 76 shows the serial interface timing diagram for a DAC38RFxx write operation. SCLK is the serial

interface clock input to DAC38RFxx. Serial data enable SDEN is an active low input to DAC38RFxx. SDIO is

serial data input. Input data to DAC38RFxx is clocked on the rising edges of SCLK.

Figure 76. Serial Interface Write Timing Diagram

Figure 77 shows the serial interface timing diagram for a DAC38RFxx read operation. SCLK is the serial

interface clock input to DAC38RFxx. Serial data enable SDEN\ is an active low input to DAC38RFxx. SDIO is

serial data input during the instruction cycle. In 3 pin configuration, SDIO is data out from the DAC38RFxx during

the data transfer cycle, while SDO is in a high-impedance state. In 4 pin configuration, both SDIO and SDO are

data out from the DAC38RFxx during the data transfer cycle. At the end of the data transfer, SDIO and SDO will

output low on the final falling edge of SCLK until the rising edge of SDEN when they will 3-state.

Figure 77. Serial Interface Read Timing Diagram

n the SIF interface there are four types of registers:

8.4.5.1 NORMAL (RW)

The NORMAL register type allows data to be written and read from. All 16-bits of the data are registered at the

same time. There is no synchronizing with an internal clock thus all register writes are asynchronous with respect

to internal clocks. There are three subtypes of NORMAL:

1. AUTOSYNC: A NORMAL register that causes a sync to be generated after the write is finished. These are

used when it is desirable to synchronize the block after writing the register or for a single field that spans

across multiple registers. For instance, the NCO requires three 16-bit register writes to set the frequency.

Upon writing the last of these registers an autosync is generated to deliver the entire field to the NCO block

at once, rather than in pieces after each individual register write. For a field that spans multiple registers, all

non-AUTOSYNC registers for the field must be written first before the actual AUTOSYNC register.

DAC38RF80 Datasheet(PDF) 78 Page - Texas Instruments

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