DAC38RF80 datasheet(52/155 Pages) TI1

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DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3C – DECEMBER 2016 – REVISED JULY 2017

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DAC38RF83 DAC38RF93

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Several important controls related to SYSREF alignment and capture timing are contained in register

SYSR_CAPTURE (8.5.78). For example, as mentioned before, the device is capable of monitoring the observed

phases of the rising SYSREF edge events; however, in order to avoid unwanted noise coupling from the

SYSREF circuits into the DAC output, the SYSREF monitoring circuits are disabled by default. Field

SYSR_STATUS_ENA enables SYSREF status monitoring. Field SYSR_PHASE_WDW contains the the phase

tolerance

window

selected

for

normal

operation,

which

optimized

during

characterization.

Field

SYSR_ALIGN_DLY contains the control that allows the system designer to optionally offset the SYSREF

alignment event by ±1 device clock cycles. Field SYSR_STATUS_ENA enables the SYSREF capture alignment

accumulation and will generate alarms when enabled. Writing a “1” to field SYSR_ALIGN_SYNC clears the

accumulated SYSREF alignment statistics. The SYSREF alignment block can be bypassed completely by field

SYSREF_BYPASS_ALIGN, in which case SYSREF is latched by the rising edge of DACCLK.

When field SYSR_STATUS_ENA is high the device records the phase associated with each SYSREF event for

use in characterizing the SYSREF capture timing and selecting an appropriate phase tolerance window. The

phase data is available in two forms. First, each of the four phases has a corresponding “sticky” alarm flag

indicating which phases have been observed since the last time the register was cleared. In addition, the device

also accumulates statistics on the relative number of occurrences of each phase spanning multiple SYSREF

events using saturating 8-bit counters. These accumulated real-time SYSREF statistics allow us to account for

time-varying effects during characterization such as potential timing differences between the 1st and Nth edges

in a “gapped” SYSREF pulse train. The counters are fields PHASE1_CNT and PHASE2_CNT in register

SYSREF12_CNT (8.5.10), PHASE3_CNT and PHASE4_CNT in register SYSREF34_CNT (8.5.11), and

ALIGN_TO_R1_CNT and ALIGN_TO_R3_CNT in register SYSREF_ALIGN_R (8.5.9).

The accumulated SYSREF statistics can be cleared by writing ‘1’ to SYSR_ALIGN_SYNC. This sync signal

affects only the SYSREF statistics monitors and does not cause a sync of any other portions of the design.

Before collecting phase statistics, the user must first enable the SYSREF status monitoring logic by setting the

SYSR_STATUS_ENA

bit.

The

user

must

then

generate

repeating

SYSREF

input

before

using

SYSR_ALIGN_SYNC to clear the statistic counters. This is necessary to flush invalid data out of the status

pipeline.

The “sticky” alarm flags indicating which of the four phases have been observed since the last

SYSR_ALIGN_SYNC write of ‘1’ are fields ALM_SYSRPHASE1 to ALM_SYSRPHASE4 and are contained in the

ALM_SYSREF_DET register (8.5.6).

8.3.11 JESD204B Subclass 0 support

Some functionality has been implemented to support Subclass 0 operation. Note that programming the

SUBCLASSV configuration parameter has no functional impact on the logic. The value programmed for

SUBCLASSV is only used in the initial lane alignment (ILA) sequence. The following configuration parameters

DAC38RF80 Datasheet(PDF) 52 Page - Texas Instruments

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