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DAC38RF80 Datasheet(PDF) 67 Page - Texas Instruments

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Part # DAC38RF80
Description  Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL
PDF  155 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

DAC38RF80 Datasheet(HTML) 67 Page - Texas Instruments

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0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
–4
–3
–2
–1
0
1
2
3
4
f/f
DAC
G056
sin(x)/x
Corrected
FIR4
_
_
2
2
u
u
CD
INPUTCD
CMIX
CD
INPUTCD
CMIX
CD
Output
I
cos
ŒI
W
4
VLQ
ŒI
W
_
_
2
2
u
u
AB
INPUTAB
CMIX
AB
INPUTAB
CMIX
AB
Output
I
cos
ŒI
W
4
VLQ
ŒI
W
67
DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
www.ti.com
SLASEA3C – DECEMBER 2016 – REVISED JULY 2017
DAC38RF83 DAC38RF93
Submit Documentation Feedback
Copyright © 2016–2017, Texas Instruments Incorporated
(5)
(6)
Where fCMIX_AB and fCMIX_CD and the fixed mixing frequency selected by fields CMIX_AB or CMIX_CD in register
CMIX (8.5.21). The coarse mixer blocks are disabled by setting CMIX_AB and CMIX_CD to 0x0.
The NCO and coarse mixers can be enabled simultaneously, although this is not useful in most cases as the full
frequency range can be covered by the NCO.
8.3.17.6 Inverse Sinc Filter
The DAC38RFxx have a 9-tap inverse Sinc filter (INVSINC) that runs at the DAC update rate (fDAC) that can be
used to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the
output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well known
sin(x)/x or Sinc(x) frequency response (Figure 67, red line). The inverse sinc filter response (Figure 67, blue line)
has the opposite frequency response from 0 to 0.4 x fDAC, resulting in the combined response (Figure 67, green
line). Between 0 to 0.4 x fDAC, the inverse sinc filter compensates the sample-and-hold roll-off with less than 0.03
dB error.
The inverse sinc filter has a gain > 1 at all frequencies. Therefore, the signal input to INVSINC must be reduced
from full scale to prevent saturation in the filter. The amount of back-off required depends on the signal
frequency, andis set such that at the signal frequencies the combination of the input signal and filter response is
less than 1 (0 dB). For example, if the signal input to INVSINC is at 0.25 x fDAC, the response of INVSINC is 0.9
dB, and the signal must be backed off from full scale by 0.9 dB to avoid saturation. The advantage of INVSINC
having a positive gain at all frequencies is that the user is then able to optimize the back-off of the signal based
on its frequency.
The inverse Sinc filters are enabled by field ISFIR_ENA in register MULTIDUC_CFG1 (9.5.9).
Figure 67. Composite Magnitude Spectrum for INVSINC
8.3.17.7 Summation Block for Dual DUC Modes
When using the dual DUC modes, the outputs of the two AQM blocks are summed together to form a composite
signal for the DAC output, configured by field OUTSUM_SEL in register OUTSUM (8.5.22). The input signals to
the DUCs much be scaled such that the signal does not exceed fullscale during summation. This field can also
be configures to add the signals from the adjacent multi-DUC to enable a four DUC signal.
8.3.18 PA Protection Block
The DAC38RFxx incorporates an optional power amplifier protection (PAP) block to monitor when the input
signal is two large, for example when an interface error occurs, and reduces the output signal power of the DAC.
The PAP block achieves the functionality of reducing the input signal that crosses the threshold through three
main sub-blocks. These are PAP trigger generation block, PAP gain state machine and GAIN block.



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