DAC38RF80 datasheet(76/155 Pages) TI1

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Fmax

min

PFD CP

Fvco

Fixed

div x Mdiv

y N

PFD

and

charge pump

Output

buffer

y 4

y M

DAC

CLK

Feedback

High VCO

Low VCO

PLL_N(4-0)

PLL_M(7-0)

DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3C – DECEMBER 2016 – REVISED JULY 2017

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DAC38RF83 DAC38RF93

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Device Functional Modes (continued)

Figure 74. Internal PLL/VCO Block Diagram

The low VCO is tuned to a target center frequency of 5.9 GHz, and the high VCO is tuned to a target center

frequency of 8.85 GHz. The VCO is selected through field PLL_VCOSEL in register PLL_CONFIG2 (8.5.81), with

‘0’ selecting the low VCO and a ‘1’ the high VCO. The 7 bit VCO tuning code in field PLL_VCO in register

PLL_CONFIG2 (8.5.81) is used to tune the VCO frequency in the range of 5.24 GHz to 6.72 GHz for low VCO

and 7.96 GHz to 9.0 GHz for the high VCO. For the low VCO the center VCO frequency is achieved with

PLL_VCO = 63decimal and for the high VCO the target VCO center frequency is achieved with PLL_VCO =

63decimal.

The supply current, and therefore; the analog signal amplitude in the VCO is controlled using the field

PLL_VCO_RDAC in register PLL_CONFIG1 (8.5.80). This control signal should be set 15decimal initially for 18 mA

supply current in the VCO and ~1.4 VPP single ended oscillation amplitude.

The PLL has no prescaler, so the DAC sample rate is the VCO frequency. In the PLL feedback path a fixed ÷ 4

frequency divider block receives the VCO output clock and divides its frequency by 4. The maximum operating

frequency of the phase-frequency detector (PFD) is approximately 550 MHz. The M (feedback) clock divider

takes the output clock signal from the fixed ÷4 block and divides it by a programmable ratio set by the 8-bit field

in field PLL_M_M1 in register PLL_CONFIG1 (8.5.80). The programmable division ratio range is ÷1 to ÷256, and

is the value of the 8 bit unsigned binary code + 1. Although it is possible to program the M divider to ÷1, ÷2 and

÷3, these values should not be used. As stated previously the PFD and CP have a finite maximum operating

frequency, which is the VCO frequency divided by the fixed divider ratio multiplied by the minimum allowable M

divider ratio.

(18)

The N (reference) divider determines the ratio between the input reference clock frequency and the PFD

operating frequency, and is set by the 5-bit field PLL_N_M1 in register CLK_PLL_CFG (8.5.79). The division ratio

range is ÷1 to ÷32, and is the value of the 5-bit unsigned binary code + 1.

DAC38RF80 Datasheet(PDF) 76 Page - Texas Instruments

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