DAC38RF80 datasheet(86/155 Pages) TI1

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DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

SLASEA3C – DECEMBER 2016 – REVISED JULY 2017

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DAC38RF83 DAC38RF93

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8.5.6 SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = 0x0000]

Figure 83. SYSREF Alignment Circuit Alarms Register (ALM_SYSREF_DET)

W0C

LEGEND: R/W = Read/Write; R = Read only; W0C = Write 0 to clear bit; -n = value after reset

Table 48. ALM_SYSREF_DET Field Descriptions

Bit

Field

Type

Reset

Description

15:9

Reserved

W0C

0000000

Reserved

ALM_SYSRPHASE4

W0C

If high the sysrefphase4 state has been observed in the

sysrefalign logic at least once since the last sysrefalign sync.

ALM_SYSRPHASE3

W0C

If high the sysrefphase3 state has been observed in the

sysrefalign logic at least once since the last sysrefalign sync.

ALM_SYSRPHASE2

W0C

If high the sysrefphase2 state has been observed in the

sysrefalign logic at least once since the last sysrefalign sync.

ALM_SYSRPHASE1

W0C

If high the sysrefphase1 state has been observed in the

sysrefalign logic at least once since the last sysrefalign sync.

ALM_ALIGN_TO_R3

W0C

If high the align_to_r3 state has been observed in the sysrefalign

logic at least once since the last sysrefalign sync. TI Internal use

only.

ALM_ALIGN_TO_R1

W0C

If high the align_to_r1 state has been observed in the sysrefalign

logic at least once since the last sysrefalign sync. TI Internal use

only.

ALM_SD0_PLL

W0C

Driven high if the PLL in the Serdes 0 block goes out of lock. A

false alarm is generated at startup when the PLL is locking. User

will have to reset this bit after start to monitor accurately.

ALM_SD1_PLL

W0C

Driven high if the PLL in the Serdes 1 block goes out of lock. A

false alarm is generated at startup when the PLL is locking. User

will have to reset this bit after start to monitor accurately.

PLL_LOCK

W0C

Asserted when PLL is unlocked.

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