DAC38RF80 datasheet(75/155 Pages) TI1

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DAC38RF80, DAC38RF83, DAC38RF84

DAC38RF85, DAC38RF90, DAC38RF93

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SLASEA3C – DECEMBER 2016 – REVISED JULY 2017

DAC38RF83 DAC38RF93

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8.3.30 DAC Transfer Function for DAC38RF80/90/84

The DAC38RF80/90/84 has a wide bandwidth integrated balun (nominally 700 MHz to 3.8 GHz passband) to

convert the DAC core differential signal to a single ended signal. The single ended output is expected to drive a

50-Ω load (see Figure 73). With full-scale current of 40 mA, the theoretical output power delivered to a 50-Ω load

is 4 dBm. However the actual power delivered will be less than the theoretical value and Figure 38 shows the

output power across frequency.

Figure 73. Driving a 50-Ω Load (DAC38RF80/90/84)

8.4 Device Functional Modes

8.4.1 Clocking Modes

The DAC38RFxx has both a single ended clock input DACCLKSE and a differential clock input DACCLK+/- to

clock the device. The clock input is selected by field SEL_EXTCLK_DIFFSE in register CLK_PLL_CFG (8.5.79).

The DAC38RFxx can be clocked directly with a high frequency input clock at the DAC sample rate (PLL Bypass

Mode), or an optional on-chip low-jitter phase-locked loop (PLL) can be used to generate the high frequency

DAC sample clock internally from a lower frequency reference clock input (PLL Mode).

8.4.2 PLL Bypass Mode Programming

In PLL bypass mode a high quality clock is sourced to the DACCLK inputs. This clock is used to directly clock

the DAC38RFxx DAC cores. This mode gives the device best performance and is recommended for extremely

demanding applications.

The bypass mode is selected by setting the following:

1. Set field PLL_ENA in register CLK_PLL_CFG (8.5.79) to “0” to bypass the PLL circuitry.

2. Set field PLL_SLEEP in register SLEEP_CONFIG (8.5.70) to “1” to put the PLL and VCO into sleep mode.

8.4.3 Internal PLL/VCO

The DAC38RFxx has an internal clock generation circuit consisting of a PLL and two selectable VCOs, as shown

in Figure 74.

DAC38RF80 Datasheet(PDF) 75 Page - Texas Instruments