PCI7510 datasheet(140/234 Pages) TI

140 / 234 page

6–7

6.5

Socket Control Register

This register provides control of the voltages applied to the socket VPP and VCC. The PCI7510 device ensures that

the socket is powered up only at acceptable voltages when a CardBus card is inserted. See Table 6–6 for a complete

description of the register contents.

Bit

Name

Socket control

Type

Default

Bit

Name

Socket control

Type

Default

Socket control

Offset:

CardBus Socket Address + 10h

Type:

Read-only, Read/Write

Default:

0000 0000h

Table 6–6. Socket Control Register Description

BIT

SIGNAL

TYPE

FUNCTION

31–12

RSVD

These bits return 0s when read.

ZV_ACTIVITY

This bit returns 0 when the ZVEN bits (bit 0) for both sockets are 0 (disabled). If either ZVEN bit is

set to 1, the ZV_ACTIVITY bit returns 1.

STANDARDZVREG

Standardized zoomed video register model supported. Because the PCI7510 device supports this

ZVEN

Zoomed video enable. This bit enables zoomed video for the socket.

RSVD

These bits return 0s when read.

STOPCLK

This bit controls how the CardBus clock run state machine decides when to stop the CardBus clock

to the CardBus card:

0 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the

sockethas been idle for 8 clocks and the PCI CLKRUN protocol is preparing to stop/slow the

PCI bus clock.

1 = The CardBus CLKRUN protocol can only attempt to stop/slow the CaredBus clock if the

socket has been idle for 8 clocks, regardless of the state of the PCI CLKRUN signal.

6–4 †

VCCCTRL

VCC control. These bits are used to request card VCC changes.

000 = Request power off (default)

100 = Request VCC = X.X V

001 = Reserved

101 = Request VCC = Y.Y V

010 = Request VCC = 5 V

110 = Reserved

011 = Request VCC = 3.3 V

111 = Reserved

RSVD

This bit returns 0 when read.

2–0 †

VPPCTRL

VPP control. These bits are used to request card VPP changes.

000 = Request power off (default)

100 = Request VPP = X.X V

001 = Request VPP = 12 V

101 = Request VPP = Y.Y V

010 = Request VPP = 5 V

110 = Reserved

011 = Request VPP = 3.3 V

111 = Reserved

† One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not

enabled, then this bit is cleared by the assertion of PRST or GRST.

PCI7510 Datasheet(PDF) 140 Page - Texas Instruments

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