PCI7510 datasheet(144/234 Pages) TI

144 / 234 page

7–3

7.3

Command Register

The command register provides control over the PCI7510 interface to the PCI bus. All bit functions adhere to the

definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7–2 for a complete

description of the register contents.

Bit

Name

Command

Type

Default

Command

Offset:

04h

Type:

Read/Write, Read-only

Default:

0000h

Table 7–2. Command Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15–11

RSVD

Reserved. Bits 15–10 return 0s when read.

INT_DISABLE

INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.

0 = INTx assertion is enabled (default)

1 = INTx assertion is disabled

This bit is disabled (read-only 0) if bit 11 (PCI2_3_EN) in the PCI miscellaneous configuration

FBB_ENB

Fast back-to-back enable. The PCI7510 device does not generate fast back-to-back transactions;

therefore, bit 9 returns 0 when read.

SERR_ENB

SERR enable. When bit 8 is set to 1, the PCI7510 SERR driver is enabled. SERR can be asserted after

detecting an address parity error on the PCI bus.

RSVD

Reserved. Bit 7 returns 0 when read.

PERR_ENB

Parity error enable. When bit 6 is set to 1, the PCI7510 device is enabled to drive PERR response to

parity errors through the PERR signal.

VGA_ENB

VGA palette snoop enable. The PCI7510 device does not feature VGA palette snooping; therefore,

bit 5 returns 0 when read.

MWI_ENB

Memory write and invalidate enable. When bit 4 is set to 1, the PCI7510 device is enabled to generate

MWI PCI bus commands. If this bit is cleared, then the PCI7510 device generates memory write

commands instead.

SPECIAL

Special cycle enable. The PCI7510 function does not respond to special cycle transactions; therefore,

bit 3 returns 0 when read.

MASTER_ENB

Bus master enable. When bit 2 is set to 1, the PCI7510 device is enabled to initiate cycles on the PCI

bus.

MEMORY_ENB

Memory response enable. Setting bit 1 to 1 enables the PCI7510 device to respond to memory cycles

on the PCI bus. This bit must be set to access OHCI registers.

IO_ENB

I/O space enable. The PCI7510 device does not implement any I/O-mapped functionality; therefore,

bit 0 returns 0 when read.

PCI7510 Datasheet(PDF) 144 Page - Texas Instruments

PCI7510 Datasheet(HTML) 144 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL