PCI7510 datasheet(207/234 Pages) TI

207 / 234 page

9–4

9.4

Link Enhancement Register

This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI

offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM,

if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software, then the bits must

be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see

Section 8.16). See Table 9–3 for a complete description of the register contents.

Bit

Name

Link enhancement

Type

Default

Bit

Name

Link enhancement

Type

RSC

Default

Link enhancement

Offset:

A88h

set register

A8Ch

clear register

Type:

Read/Set/Clear, Read-only

Default:

0000 0000h

Table 9–3. Link Enhancement Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31–16

RSVD

Reserved. Bits 31–16 return 0s when read.

dis_at_pipeline

RSC

Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled.

RSVD

Reserved.

13–12

atx_thresh

RSC

This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the

PCI7510 device retries the packet, it uses a 2K-byte threshold, resulting in a store-and-forward

operation.

00 = Threshold ~ 2K bytes resulting in a store-and-forward operation

01 = Threshold ~ 1.7K bytes (default)

10 = Threshold ~ 1K bytes

11 = Threshold ~ 512 bytes

These bits fine-tune the asynchronous transmit threshold. For most applications the 1.7K-byte

threshold is optimal. Changing this value may increase or decrease the 1394 latency depending on

the average PCI bus latency.

Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds

or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger

than the AT threshold, then the remaining data must be received before the AT FIFO is emptied;

otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. As a result,

the link then commences store-and-forward operation. Wait until it has the complete packet in the

FIFO before retransmitting it on the second attempt, to ensure delivery.

An AT threshold of 2K results in store-and-forward operation, which means that asynchronous data

will not be transmitted until an end-of-packet token is received. Restated, setting the AT threshold

to 2K results in only complete packets being transmitted.

Note that this device always uses store-and-forward when the asynchronous transmit retries register

at OHCI offset 08h (see Section 8.3) is cleared.

RSVD

Reserved. Bit 11 returns 0 when read.

enab_mpeg_ts

RSC

Enable MPEG timestamp enhancements. When bit 10 is set to 1, the enhancement is enabled for

MPEG transmit streams (FMT = 20h).

RSVD

Reserved. Bit 9 returns 0 when read.

enab_dv_ts

RSC

Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV

CIP transmit streams (FMT = 00h).

PCI7510 Datasheet(PDF) 207 Page - Texas Instruments

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