CS5530A datasheet(177/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

177

Revision 1.1

6:0

Mask

If bit 7 = 0 (I/O):

Bit 6

0 = Disable write cycle tracking

1 = Enable write cycle tracking

Bit 5

0 = Disable read cycle tracking

1 = Enable read cycle tracking

Bits 4:0

Mask for address bits A[4:0]

If bit 7 = 1 (M/IO):

Bits 6:0

Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored.

Note: A “1” in a mask bit means that the address bit is ignored for comparison.

Index CFh

Reserved

Reset Value = xxh

Index D0h

Software SMI Register (WO)

Reset Value = 00h

7:0

Software SMI (Write Only): A write to this location generates an SMI. The data written is irrelevant. This register allows

software entry into SMM via normal bus access instructions.

Index D1h-EBh

Reserved

Reset Value = xxh

Index ECh

Timer Test Register (R/W)

Reset Value = 00h

7:0

Timer Test Value: The Timer Test Register is intended only for test and debug purposes. It is not intended for setting oper-

ational timebases.

Index EDh-F3h

Reserved

Reset Value = xxh

Index F4h

Second Level Power Management Status Register 1 (RC)

Reset Value = 00h

7:5

Reserved

Game Port SMI Status (Read to Clear): SMI was caused by a R/W access to game port (I/O Port 200h and 201h)?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

Game Port Read SMI generation enabling is at F0 Index 83h[4].

Game Port Write SMI generation enabling is at F0 Index 53h[3].

GPIO7 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO7 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[3].

GPIO5 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO5 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[2].

GPIO4 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO4 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[1].

GPIO3 SMI Status (Read to Clear): SMI was caused by transition on (properly-configured) GPIO3 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[0].

Note: Properly-configured means that the GPIO pin must be enabled as a GPIO, an input, and to cause an SMI.

This register provides status on various power-management SMI events. Reading this register clears the SMI status bits. A read-

only (mirror) version of this register exists at F0 Index 84h.

Index F5h

Second Level Power Management Status Register 2 (RC)

Reset Value = 00h

Video Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the Video Idle Timer Count Register

(F0 Index A6h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[7].

User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read to Clear): SMI was caused by expiration of the UDEF3 Idle

Timer Count Register (F0 Index A4h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[6].

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 177 Page - Advanced Micro Devices

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