CS5530A datasheet(174/259 Pages) AMD

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174

AMD Geode™ CS5530A Companion Device Data Book

Revision 1.1

Index AFh

Suspend Notebook Command Register (WO)

Reset Value = 00h

7:0

Software CPU Stop Clock Suspend (Write Only): A write to this register causes a SUSP#/SUSPA# handshake with the

CPU, placing the CPU in a low-power state. Following this handshake, the SUSP_3V pin is asserted. The SUSP_3V pin is

intended to be used to stop all system clocks.

Upon a Resume event (see Note), the SUSP_3V pin is deasserted. After a slight delay, the CS5530A deasserts the SUSP#

signal. Once the clocks are stable, the processor deasserts SUSPA# and system operation resumes.

Note: If the clocks are stopped the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the

only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI

source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wake-

up the system from Suspend when the clocks are stopped.

Index B0h-B3h

Reserved

Reset Value = xxh

Index B4h

Floppy Port 3F2h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 3F2h Shadow (Read Only): Last written value of I/O Port 3F2h. Required for support of FDC power ON/OFF

and Save-to-Disk/RAM coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B5h

Floppy Port 3F7h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 3F7h Shadow (Read Only): Last written value of I/O Port 3F7h. Required for support of FDC power ON/OFF

and Save-to-Disk/RAM coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B6h

Floppy Port 1F2h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 1F2h Shadow (Read Only): Last written value of I/O Port 1F2h. Required for support of FDC power ON/OFF

and Save-to-Disk/RAM coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B7h

Floppy Port 1F7h Shadow Register (RO)

Reset Value = xxh

7:0

Floppy Port 1F7h Shadow (Read Only): Last written value of I/O Port 1F7h. Required for support of FDC power ON/OFF

and Save-to-Disk/RAM coherency.

This register is a copy of an I/O register which cannot safely be directly read. Value in register is not deterministic of when

the register is being read. It is provided here to assist in a Save-to-Disk operation.

Index B8h

DMA Shadow Register (RO)

Reset Value = xxh

7:0

DMA Shadow (Read Only): This 8-bit port sequences through the following list of shadowed DMA Controller registers. At

power on, a pointer starts at the first register in the list and consecutively reads incrementally through it. A write to this reg-

ister resets the read sequence to the first register. Each shadow register in the sequence contains the last data written to

that location.

The read sequence for this register is:

1. DMA Channel 0 Mode Register

2. DMA Channel 1 Mode Register

3. DMA Channel 2 Mode Register

4. DMA Channel 3 Mode Register

5. DMA Channel 4 Mode Register

6. DMA Channel 5 Mode Register

7. DMA Channel 6 Mode Register

8. DMA Channel 7 Mode Register

9. DMA Channel Mask Register (bit 0 is channel 0 mask, etc.)

10. DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1 ms, all other bits are 0)

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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