CS5530A datasheet(170/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Revision 1.1

GPIO1 Edge Sense for SMI: Selects which edge transition of the GPIO1 pin generates an SMI. 0 = Rising; 1 = Falling.

Bit 1 must be set to enable this bit.

GPIO0 Edge Sense for SMI: Selects which edge transition of the GPIO0 pin generates an SMI. 0 = Rising; 1 = Falling.

Bit 1 must be set to enable this bit.

Enable GPIO2 as an External SMI Source: Allow GPIO2 to be an external SMI source and generate an SMI on either a

rising or falling edge transition (depends upon setting of bit 5). 0 = Disable; 1 = Enable (Note 3).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 87h/F7h[7].

Enable GPIO1 as an External SMI Source: Allow GPIO1 to be an external SMI source and generate an SMI on either a

rising- or falling-edge transition (depends upon setting of bit 4). 0 = Disable; 1 = Enable (Note 3).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 87h/F7h[6].

Enable GPIO0 as an External SMI Source: Allow GPIO0 to be an external SMI source and generate an SMI on either a

rising or falling edge transition (depends upon setting of bit 3). 0 = Disable; 1 = Enable (Note 3)

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 87h/F7h[5].

Notes: 1) For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h).

2) GPIO7 can generate an SMI (F0 Index 97h[3]) or re-trigger General Purpose Timer 2 (F0 Index 8Bh[2]) or both.

3) If GPIO[2:0] are enabled as external SMI sources, they are the only GPIOs that can be used as SMI sources to wake-up the

system from Suspend when the clocks are stopped.

Index 93h

Miscellaneous Device Control Register (R/W)

Reset Value = 00h

Floppy Drive Port Select: All system resources used to power manage the floppy drive use the primary or secondary FDC

addresses for decode. 0 = Primary; 1 = Primary and Secondary.

Reserved: This bit must always be set to 1.

Partial Primary Hard Disk Decode: This bit is used to restrict the addresses which are decoded as primary hard disk

accesses.

0 = Power management monitors all reads and writes I/O Port 1F0h-1F7h, 3F6h

1 = Power management monitors only writes to I/O Port 1F6h and 1F7h

Partial Secondary Hard Disk Decode: This bit is used to restrict the addresses which are decoded as secondary hard

Disk accesses.

0 = Power management monitors all reads and writes I/O Port 170h-177h, 376h

1 = Power management monitors only writes to I/O Port 176h and 177h

3:2

Reserved: Set to 0.

Mouse on Serial Enable: Mouse is present on a serial port. 0 = No; 1 = Yes. (Note)

Mouse Port Select: Selects which serial port the mouse is attached to. 0 = COM1; 1 = COM2. (Note)

Note: Bits 1 and 0 - If a mouse is attached to a serial port (bit 1 = 1), that port is removed from the serial device list being used to

monitor serial port access for power management purposes and added to the keyboard/mouse decode. This is done because a

mouse, along with the keyboard, is considered an input device and is used only to determine when to blank the screen.

These bits determine the decode used for the Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) as well as the Parallel/

Serial Port Idle Timer Count Register (F0 Index 9Ch).

Index 94h

Suspend Modulation OFF Count Register (R/W)

Reset Value = 00h

7:0

Suspend Signal Deasserted Count: This 8-bit value represents the number of 32 µs intervals that the SUSP# pin will be

deasserted to the GX1 processor. This timer, together with the Suspend Modulation ON Count Register (F0 Index 95h), per-

form the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective

(emulated) clock frequency, allowing the power manager to reduce CPU power consumption.

This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video

speedups.

Index 95h

Suspend Modulation ON Count Register (R/W)

Reset Value = 00h

7:0

Suspend Signal Asserted Count: This 8-bit value represents the number of 32 µs intervals that the SUSP# pin will be

asserted. This timer, together with the Suspend Modulation OFF Count Register (F0 Index 94h), perform the Suspend Mod-

ulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock fre-

quency, allowing the power manager to reduce CPU power consumption.

This timer is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video

speedups.

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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