CS5530A datasheet(171/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

171

Revision 1.1

Index 96h

Suspend Configuration Register (R/W)

Reset Value = 00h

7:5

Reserved: Set to 0.

Power Savings Mode: 0 = Enable; 1 = Disable.

Include ISA Clock in Power Savings Mode: 0 = ISA clock not included; 1 = ISA clock included.

Suspend Mode Configuration: “Special 3 Volt Suspend” mode to support powering down the GX1 processor during Sus-

pend. 0 = Disable; 1 = Enable.

SMI Speedup Configuration: Selects how Suspend Modulation function reacts when an SMI occurs.

0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI

occurs.

1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory

Offset 08h).

The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA

technology and power management operations occur at full speed. Two methods for accomplishing this are either to map

the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until

the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method.

The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530A. This bit has no effect

if the Suspend Modulation feature is disabled (bit 0 = 0).

Suspend Modulation Feature: 0 = Disable; 1 = Enable.

When enabled, the SUSP# pin will be asserted and deasserted for the durations programmed in the Suspend Modulation

OFF/ON Count Registers (F0 Index 94h/95h).

Index 97h

GPIO Control Register 2 (R/W)

Reset Value = 00h

GPIO7 Edge Sense for SMI: Selects which edge transition of the GPIO7 pin generates an SMI. 0 = Rising; 1 = Falling.

Bit 3 must be set to enable this bit.

GPIO5 Edge Sense for SMI: Selects which edge transition of the GPIO5 pin generates an SMI. 0 = Rising; 1 = Falling.

Bit 2 must be set to enable this bit.

GPIO4 Edge Sense for SMI: Selects which edge transition of the GPIO4 pin generates an SMI. 0 = Rising; 1 = Falling.

Bit 1 must be set to enable this bit.

GPIO3 Edge Sense for SMI: Selects which edge transition of the GPIO3 pin generates an SMI. 0 = Rising; 1 = Falling.

Bit 0 must be set to enable this bit.

Enable GPIO7 as an External SMI Source: Allow GPIO7 to be an external SMI source and to generate an SMI on either a

rising or falling edge transition (depends upon setting of bit 7). 0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 84h/F4h[3].

Enable GPIO5 as an External SMI Source: Allow GPIO5 to be an external SMI source and to generate an SMI on either a

rising or falling edge transition (depends upon setting of bit 6). 0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 84h/F4h[2].

Enable GPIO4 as an External SMI Source: Allow GPIO4 to be an external SMI source and to generate an SMI on either a

rising- or falling-edge transition (depends upon setting of bit 5). 0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 84h/F4h[1].

Enable GPIO3 as an External SMI Source: Allow GPIO3 to be an external SMI source and to generate an SMI on either a

rising or falling edge transition (depends upon setting of bit 4) 0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status reporting is at F0 Index 84h/F4h[0].

Note: For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h).

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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