CS5530A datasheet(172/259 Pages) AMD

172 / 259 page

172

AMD Geode™ CS5530A Companion Device Data Book

Revision 1.1

Index 98h-99h

Primary Hard Disk Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Primary Hard Disk Idle Timer Count: The idle timer loaded from this register is used to determine when the primary hard

disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of primary hard

disk inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value when-

ever an access occurs to the configured primary hard disk’s data port (configured in F0 Index 93h[5]). The timer uses a 1

second timebase.

To enable this timer set F0 Index 81h[0] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[0].

Index 9Ah-9Bh

Floppy Disk Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Floppy Disk Idle Timer Count: The idle timer loaded from this register is used to determine when the floppy disk drive is

not in use so that it can be powered down. The 16-bit value programmed here represents the period of floppy disk drive

inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an

access occurs to any of I/O Ports 3F2h, 3F4h, 3F5h, and 3F7h (primary) or 372h, 374h, 375h, and 377h (secondary). The

timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[1] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[1].

Index 9Ch-9Dh

Parallel / Serial Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Parallel / Serial Idle Timer Count: The idle timer loaded from this register is used to determine when the parallel and serial

ports are not in use so that the ports can be power managed. The 16-bit value programmed here represents the period of

inactivity for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count

value whenever an access occurs to the parallel (LPT) or serial (COM) I/O address spaces. If the mouse is enabled on a

serial port, that port is not considered here. The timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[2] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[2].

Index 9Eh-9Fh

Keyboard / Mouse Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Keyboard / Mouse Idle Timer Count: The idle timer loaded from this register determines when the keyboard and mouse

are not in use so that the LCD screen can be blanked. The 16-bit value programmed here represents the period of inactivity

for these ports after which the system is alerted via an SMI. The timer is automatically reloaded with the count value when-

ever an access occurs to either the keyboard or mouse I/O address spaces, including the mouse serial port address space

when a mouse is enabled on a serial port. The timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[3] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[3].

Index A0h-A1h

User Defined Device 1 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 1 (UDEF1) Idle Timer Count: The idle timer loaded from this register determines when the device

configured as UDEF1 is not in use so that it can be power managed. The 16-bit value programmed here represents the

period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the

count value whenever an access occurs to memory or I/O address space configured at F0 Index C0h (base address regis-

ter) and F0 Index CCh (control register). The timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[4] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[4].

Index A2h-A3h

User Defined Device 2 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 2 (UDEF2) Idle Timer Count: The idle timer loaded from this register determines when the device

configured as UDEF2 is not in use so that it can be power managed. The 16-bit value programmed here represents the

period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the

count value whenever an access occurs to memory or I/O address space configured at F0 Index C4h (base address regis-

ter) and F0 Index CDh (control register). The timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[5] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[5].

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 172 Page - Advanced Micro Devices

CS5530A Datasheet(HTML) 172 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL