CS5530A datasheet(173/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

173

Revision 1.1

Index A4h-A5h

User Defined Device 3 Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

User Defined Device 3 (UDEF3) Idle Timer Count: The idle timer loaded from this register determines when the device

configured as UDEF3 is not in use so that it can be power managed. The 16-bit value programmed here represents the

period of inactivity for this device after which the system is alerted via an SMI. The timer is automatically reloaded with the

count value whenever an access occurs to memory or I/O address space configured at F0 Index C8h (base address regis-

ter) and F0 Index CEh (control register). The timer uses a 1 second timebase.

To enable this timer set F0 Index 81h[6] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[6].

Index A6h-A7h

Video Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Video Idle Timer Count: The idle timer loaded from this register determines when the graphics subsystem has been idle as

part of the Suspend determination algorithm. The 16-bit value programmed here represents the period of video inactivity

after which the system is alerted via an SMI. The count in this timer is automatically reset whenever an access occurs to the

graphics controller space. The timer uses a 1 second timebase.

In a GX1 processor based system the graphics controller is embedded in the CPU, so video activity is communicated to the

CS5530A via the serial connection (PSERIAL register, bit 0) from the processor. The CS5530A also detects accesses to

standard VGA space on PCI (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) in the event an external VGA controller is being used.

To enable this timer set F0 Index 81h[7] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[7].

Index A8h-A9h

Video Overflow Count Register (R/W)

Reset Value = 0000h

15:0

Video Overflow Count: Each time the Video Speedup timer (F0 Index 8Dh) is triggered, a 100 ms timer is started. If the

100 ms timer expires before the Video Speedup timer lapses, the Video Overflow Count Register increments and the 100

ms timer re-triggers. Software clears the overflow register when new evaluations are to begin. The count contained in this

Index AAh-ABh

Reserved

Reset Value = xxh

Index ACh-ADh

Secondary Hard Disk Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Secondary Hard Disk Idle Timer Count: The idle timer loaded from this register is used to determine when the secondary

hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of second-

ary hard disk inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value

whenever an access occurs to the configured secondary hard disk’s data port (configured in F0 Index 93h[4]). The timer

uses a 1 second timebase.

To enable this timer set F0 Index 83h[7] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[4].

Index AEh

CPU Suspend Command Register (WO)

Reset Value = 00h

7:0

Software CPU Suspend Command (Write Only): If bit 0 in the Clock Stop Control Register is set low (F0 Index BCh[0] =

0) and all SMI status bits are 0, a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU

in a low-power state. The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt con-

dition.

If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the SUSP_3V pin is asserted after

the SUSP#/SUSPA# halt. Upon a Resume event (see Note), the PLL delay programmed in the F0 Index BCh[7:4] is invoked,

allowing the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.

Note: If the clocks are stopped, the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are the

only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external SMI

source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530A pins can be used to wake-

up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active, internal SMI

events are also Resume events.

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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