CS5530A datasheet(175/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

175

Revision 1.1

Index B9h

PIC Shadow Register (RO)

Reset Value = xxh

7:0

PIC Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interrupt Con-

troller registers. At power on, a pointer starts at the first register in the list and consecutively reads incrementally through it.

A write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last

data written to that location.

The read sequence for this register is:

1. PIC1 ICW1

2. PIC1 ICW2

3. PIC1 ICW3

4. PIC1 ICW4 - Bits [7:5] of ICW4 are always 0

5. PIC1 OCW2 - Bits [6:3] of OCW2 are always 0 (Note)

6. PIC1 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1

7. PIC2 ICW1

8. PIC2 ICW2

9. PIC2 ICW3

10. PIC2 ICW4 - Bits [7:5] of ICW4 are always 0

11. PIC2 OCW2 - Bits [6:3] of OCW2 are always 0 (Note)

12. PIC2 OCW3 - Bits [7, 4] are 0 and bit [6, 3] are 1

Note: To restore OCW2 to shadow register value, write the appropriate address twice. First with the shadow register value,

then with the shadow register value ORed with C0h.

Index BAh

PIT Shadow Register (RO)

Reset Value = xxh

7:0

PIT Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interval Timer

registers. At power on, a pointer starts at the first register in the list and consecutively reads to increment through it. A write

to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last data

written to that location.

The read sequence for this register is:

1. Counter 0 LSB (least significant byte)

2. Counter 0 MSB

3. Counter 1 LSB

4. Counter 1 MSB

5. Counter 2 LSB

6. Counter 2 MSB

7. Counter 0 Command Word

8. Counter 1 Command Word

9. Counter 2 Command Word

Note: The LSB/MSB of the count is the Counter base value, not the current value.

Bits [7:6] of the command words are not used.

Index BBh

RTC Index Shadow Register (RO)

Reset Value = xxh

7:0

RTC Index Shadow (Read Only): The RTC Shadow register contains the last written value of the RTC Index

Index BCh

Clock Stop Control Register (R/W)

Reset Value = 00h

7:4

PLL Delay: The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the SUSP#

pin is deasserted to the CPU. This delay is designed to allow the clock chip and CPU PLL to stabilize before starting execu-

tion. This delay is only invoked if the STP_CLK bit (bit 0) was set.

The four-bit field allows values from 0 to 15 ms.

0000 = 0 ms

0100 = 4 ms

1000 = 8 ms

1100 = 12 ms

0001 = 1 ms

0101 = 5 ms

1001 = 9 ms

1101 = 13 ms

0010 = 2 ms

0110 = 6 ms

1010 = 10 ms

1110 = 14 ms

0011 = 3 ms

0111 = 7 ms

1011 = 11 ms

1111 = 15 ms

3:1

Reserved: Set to 0.

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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