CS5530A datasheet(176/259 Pages) AMD

176 / 259 page

176

AMD Geode™ CS5530A Companion Device Data Book

Revision 1.1

CPU Clock Stop: 0 = Normal SUSP#/ SUSPA# handshake; 1 = Full system Suspend.

Note: This register configures the CS5530A to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the

appropriate conditions, stopping the system clocks. A delay of 0 to 15 ms is programmable (bits 7:4) to allow for a delay for the

clock chip and CPU PLL to stabilize when an event Resumes the system.

A write to the CPU Suspend Command Register (F0 Index AEh) with bit 0 written as:

0 = SUSP#/SUSPA# handshake occurs. The CPU is put into a low-power state, and the system clocks are not stopped. When a

break/resume event occurs, it releases the CPU halt condition.

1 = SUSP#/SUSPA# handshake occurs and the SUSP_3V pin is asserted, thus invoking a full system Suspend (both CPU and

system clocks are stopped). When a break event occurs, the SUSP_3V pin will deassert, the PLL delay programmed in bits [7:4]

will be invoked which allows the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.

Index BDh-BFh

Reserved

Reset Value = xxh

Index C0h-C3h

User Defined Device 1 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 1 (UDEF1) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compara-

tor for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh).

Index C4h-C7h

User Defined Device 2 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 2 (UDEF2) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compara-

tor for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh).

Index C8h-CBh

User Defined Device 3 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 3 (UDEF3) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compara-

tor for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh).

Index CCh

User Defined Device 1 Control Register (R/W)

Reset Value = 00h

Memory or I/O Mapped: User Defined Device 1 is: 0 = I/O; 1 = Memory.

6:0

Mask

If bit 7 = 0 (I/O):

Bit 6

0 = Disable write cycle tracking

1 = Enable write cycle tracking

Bit 5

0 = Disable read cycle tracking

1 = Enable read cycle tracking

Bits 4:0

Mask for address bits A[4:0]

If bit 7 = 1 (M/IO):

Bits 6:0

Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored.

Note: A “1” in a mask bit means that the address bit is ignored for comparison.

Index CDh

User Defined Device 2 Control Register (R/W)

Reset Value = 00h

Memory or I/O Mapped: User Defined Device 2 is: 0 = I/O; 1 = Memory.

6:0

Mask

If bit 7 = 0 (I/O):

Bit 6

0 = Disable write cycle tracking

1 = Enable write cycle tracking

Bit 5

0 = Disable read cycle tracking

1 = Enable read cycle tracking

Bits 4:0

Mask for address bits A[4:0]

If bit 7 = 1 (M/IO):

Bits 6:0

Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored.

Note: A “1” in a mask bit means that the address bit is ignored for comparison.

Index CEh

User Defined Device 3 Control Register (R/W)

Reset Value = 00h

Memory or I/O Mapped: User Defined Device 3 is: 0 = I/O; 1 = Memory.

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 176 Page - Advanced Micro Devices

CS5530A Datasheet(HTML) 176 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL