CS5530A datasheet(169/259 Pages) AMD

169 / 259 page

AMD Geode™ CS5530A Companion Device Data Book

169

Revision 1.1

Index 8Dh

Video Speedup Timer Count Register (R/W)

Reset Value = 00h

7:0

Video Speedup Timer Count: This register holds the load value for the Video speedup timer. It is loaded into the timer

when Suspend Modulation is enabled (F0 Index 96h[0] = 1) and any access to the graphics controller occurs. When a video

access occurs, the Suspend Modulation logic is inhibited, permitting full-performance operation of the CPU. Upon expira-

tion, no SMI is generated; the Suspend Modulation begins again. The video speedup timer’s timebase is 1 ms.

This speedup mechanism allows instantaneous response to video activity for full speed during video processing calcula-

tions. A typical value here would be 50 to 100 ms.

Index 8Eh

VGA Timer Count Register (R/W)

Reset Value = 00h

7:0

VGA Timer Load Value: This register holds the load value for the VGA timer. The value is loaded into the timer when the

timer is enabled (F0 Index 83h[3] = 1). The timer is decremented with each clock of the configured timebase (F0 Index

8Bh[6]). Upon expiration of the timer, an SMI is generated and the status is reported in F1BAR+Memory Offset 00h/02h[6]

(only). Once expired, this timer must be re-initialized by disabling it (F0 Index 83h[3] = 0) and then enabling it (F0 Index

83h[3] = 1). When the count value is changed in this register, the timer must be re-initialized in order for the new value to be

loaded.

This timer’s timebase is selectable as 1 ms (default) or 32 µs. (F0 Index 8Bh).

Note: Although grouped with the power management Idle Timers, the VGA Timer is not a power management function. It is

not affected by the Global Power Management Enable setting at F0 Index 80h[0].

Index 8Fh

Reserved

Reset Value = xxh

Index 90h

GPIO Pin Direction Register 1 (R/W)

Reset Value = 00h

GPIO7 Direction: Selects if GPIO7 is an input or output. 0 = Input; 1 = Output.

GPIO6 Direction: Selects if GPIO6 is an input or output. 0 = Input; 1 = Output.

GPIO5 Direction: Selects if GPIO5 is an input or output. 0 = Input; 1 = Output.

GPIO4 Direction: Selects if GPIO4 is an input or output. 0 = Input; 1 = Output.

GPIO3 Direction: Selects if GPIO3 is an input or output. 0 = Input; 1 = Output.

GPIO2 Direction: Selects if GPIO2 is an input or output. 0 = Input; 1 = Output.

GPIO1 Direction: Selects if GPIO1 is an input or output. 0 = Input; 1 = Output.

GPIO0 Direction: Selects if GPIO0 is an input or output. 0 = Input; 1 = Output.

Note: Several of these pins have specific alternate functions. The direction configured here must be consistent with the pins’ use as the

alternate function.

Index 91h

GPIO Pin Data Register 1 (R/W)

Reset Value = 00h

GPIO7 Data: Reflects the level of GPIO7. 0 = Low; 1 = High.

GPIO6 Data: Reflects the level of GPIO6. 0 = Low; 1 = High.

GPIO5 Data: Reflects the level of GPIO5. 0 = Low; 1 = High.

GPIO4 Data: Reflects the level of GPIO4. 0 = Low; 1 = High.

GPIO3 Data: Reflects the level of GPIO3. 0 = Low; 1 = High.

GPIO2 Data: Reflects the level of GPIO2. 0 = Low; 1 = High.

GPIO1 Data: Reflects the level of GPIO1. 0 = Low; 1 = High.

GPIO0 Data: Reflects the level of GPIO0. 0 = Low; 1 = High.

Note: This register contains the direct values of GPIO[7:0] pins. Write operations are valid only for bits defined as output. Reads from

this register read the last written value if the pin is an output. The pins are configured as inputs or outputs in F0 Index 90h.

Index 92h

GPIO Control Register 1 (R/W)

Reset Value = 00h

GPIO7 Edge Sense for Reload of General Purpose Timer 2: Selects which edge transition of GPIO7 causes

GP Timer 2 to reload. 0 = Rising; 1 = Falling (Note 2).

GPIO6 Enabled as Lid Switch: Allow GPIO6 to act as the lid switch input. 0 = GPIO6; 1 = Lid switch.

When enabled, every transition of the GPIO6 pin causes the lid switch status to toggle and generate an SMI.

The top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 87h/F7h[3].

If GPIO6 is enabled as the lid switch, F0 Index 87h/F7h[4] reports the current status of the lid’s position.

GPIO2 Edge Sense for SMI: Selects which edge transition of the GPIO2 pin generates an SMI. 0 = Rising; 1 = Falling.

Bit 2 must be set to enable this bit.

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

CS5530A Datasheet(PDF) 169 Page - Advanced Micro Devices

CS5530A Datasheet(HTML) 169 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL