CS5530A datasheet(166/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Revision 1.1

Parallel/Serial Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Parallel/Serial Port Idle Timer

Count Register (F0 Index 9Ch)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[2].

Floppy Disk Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Floppy Disk Idle Timer Count Reg-

ister (F0 Index 9Ah)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[1].

Primary Hard Disk Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Primary Hard Disk Idle Timer

Count Register (F0 Index 98h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[0].

Note: This register provides status on the Device Idle Timers to the SMI handler. A bit set here indicates that the device was idle for the

duration configured in the Idle Timer Count register for that device, causing an SMI. It is called a Mirror register since an identical

register exists at F0 Index F5h. Reading this register does not clear the status, while reading its counterpart at F0 Index F5h does

clear the status.

Index 86h

Second Level Power Management Status Mirror Register 3 (RO)

Reset Value = 00h

Video Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to the Video I/O Trap?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 82h[7].

Reserved (Read Only)

Secondary Hard Disk Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to the

secondary hard disk? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 83h[6].

Secondary Hard Disk Idle Timer SMI Status (Read Only): SMI was caused by expiration of Hard Disk Idle Timer Count

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 83h[7].

Keyboard/Mouse Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to the keyboard or

mouse? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 82h[3].

Parallel/Serial Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to either the serial or

parallel ports? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 82h[2].

Floppy Disk Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to the floppy disk?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 82h[1].

Primary Hard Disk Access Trap SMI Status (Read Only): SMI was caused by a trapped I/O access to the primary hard

disk? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 82h[0].

Note: This register provides status on the Device Traps to the SMI handler. A bit set here indicates that an access occurred to the

device while the trap was enabled, causing an SMI. It is called a Mirror register since an identical register exists at F0 Index F6h.

Reading this register does not clear the status, while reading its counterpart at F0 Index F6h does clear the status.

Index 87h

Second Level Power Management Status Mirror Register 4 (RO)

Reset Value = 00h

GPIO2 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO2 pin? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 92h[2].

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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