CS5530A datasheet(164/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Revision 1.1

Parallel/Serial Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated.

LPT1: I/O Port 378h-37Fh, 778h-77Ah

LPT2: I/O Port 278h-27Fh, 678h-67Ah

COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded)

COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded)

COM3: I/O Port 3E8h-3EFh

COM4: I/O Port 2E8h-2EFh

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[2].

Floppy Disk Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated.

Primary floppy disk: I/O Port 3F2h, 3F4h, 3F5h, or 3F7

Secondary floppy disk: I/O Port 372h, 373h, 375h, or 377h

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[1].

Primary Hard Disk Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[5], an SMI is generated.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[0].

Index 83h

Power Management Enable Register 4 (R/W)

Reset Value = 00h

Secondary Hard Disk Idle Timer Enable: Load timer from Secondary Hard Disk Idle Timer Count Register (F0 Index ACh)

and generate an SMI when the timer expires. 0 = Disable; 1 = Enable.

If an access occurs in the address ranges selected in F0 Index 93h[4], the timer is reloaded with the programmed count.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[4].

Secondary Hard Disk Trap: 0 = Disable; 1 = Enable.

If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[4], an SMI is generated.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[5].

ACPI Timer SMI: Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR+Memory Offset 1Ch or I/O Port

121Ch). 0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 87h/F7h[0].

Game Port Read SMI: Allow SMI generation on reads to game port (I/O Port 200h and 201h).

0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 84h/F4h[4].

For “Game Port Write SMI” see F0 Index 53h[3].

VGA Timer Enable: Turn on VGA Timer and generate an SMI when the timer reaches 0. 0 = Disable; 1 = Enable.

VGA Timer programming is at F0 Index 8Eh and F0 Index 8Bh[6].

To reload the count in the VGA timer, disable it, optionally change the count value in F0 Index 8Eh[7:0], and reenable it

before enabling power management.

SMI Status reporting is at F1BAR+Memory Offset 00h/02h[6] (only).

Although grouped with the power management Idle Timers, the VGA Timer is not a power management function. The VGA

Timer counts whether power management is enabled or disabled.

Video Retrace Interrupt SMI: Allow SMI generation whenever video retrace occurs. 0 = Disable; 1 = Enable.

This information is decoded from the serial connection (PSERIAL register, bit 7) from the GX1 processor. This function is

normally not used for power management but for softVGA routines.

SMI status reporting is at F1BAR+Memory Offset 00h/02h[5] (only).

General Purpose Timer 2 (GP Timer 2) Enable: Turn on GP Timer 2 and generate an SMI when the timer expires.

0 = Disable; 1 = Enable.

This idle timer is reloaded from the assertion of GPIO7 (if programmed to do so). GP Timer 2 programming is at F0 Index

8Ah and 8Bh[5,3,2].

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9].

Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[1].

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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