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CS5530A Datasheet(PDF) 161 Page - Advanced Micro Devices |
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CS5530A Datasheet(HTML) 161 Page - Advanced Micro Devices |
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161 / 259 page  AMD Geode™ CS5530A Companion Device Data Book 161 Register Descriptions Revision 1.1 3:0 INTA# Target Interrupt: Selects target interrupt for INTA#. 0000 = Disable 0100 = IRQ4 1000 = RSVD ‘ 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility. Index 5Dh PCI Interrupt Steering Register 2 (R/W) Reset Value = 00h 7:4 INTD# Target Interrupt: Selects target interrupt for INTD#. 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 3:0 INTC# Target Interrupt: Selects target interrupt for INTC#. 0000 = Disable 0100 = IRQ4 1000 = RSVD 1100 = IRQ12 0001 = IRQ1 0101 = IRQ5 1001 = IRQ9 1101 = RSVD 0010 = RSVD 0110 = IRQ6 1010 = IRQ10 1110 = IRQ14 0011 = IRQ3 0111 = IRQ7 1011 = IRQ11 1111 = IRQ15 Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI interrupt compatibility. Index 5Eh-6Fh Reserved Reset Value = xxh Index 70h-71h General Purpose Chip Select Base Address Register (R/W) Reset Value = 0000h 15:0 General Purpose Chip Select I/O Base Address: This 16-bit value represents the I/O base address used to enable the assertion of the GPCS# signal. This register, together with General Purpose Chip Select Control Register (F0 Index 72h) is used to configure the operation of the GPCS# pin. Index 72h General Purpose Chip Select Control Register (R/W) Reset Value = 00h 7 General Purpose Chip Select: GPCS# (pin AF26). 0 = Disable; 1 = Enable. If the GPCS# signal is disabled (i.e., this bit = 0) its output is permanently driven high. 6 Writes Result in Chip Select: Writes to configured I/O address (base address configured in F0 Index 70h and range con- figured in bits [4:0]) causes GPCS# signal to be asserted. 0 = Disable; 1 = Enable. 5 Reads Result in Chip Select: Reads from configured I/O address (base address configured in F0 Index 70h and range configured in bits [4:0]) causes GPCS# signal to be asserted. 0 = Disable; 1 = Enable. 4:0 General Purpose Chip Select I/O Address Range: This 5-bit field selects the range of GPCS# signal. 00000 = 1 byte 01111 = 16 bytes 00001 = 2 bytes 11111 = 32 bytes 00011 = 4 bytes All other combinations are reserved. 00111 = 8 bytes Note: This register, together with General Purpose Chip Select Base Address Register (F0 Index 70h) is used to configure the opera- tion of the GPCS# pin. Index 73h-7Fh Reserved Reset Value = xxh Index 80h Power Management Enable Register 1 (R/W) Reset Value = 00h 7:6 Reserved: Set to 0. 5 Codec SDATA_IN SMI: Allow AC97 codec to generate an SMI due to codec producing a positive edge on SDATA_IN. 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[2]. 4 Video Speedup: Any video activity, as decoded from the serial connection (PSERIAL register, bit 0) from the GX1 proces- sor disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when the system is power man- aged using CPU Suspend modulation. 0 = Disable; 1 = Enable. The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an external VGA access (3Bxh, 3Cxh, 3Dxh and A000h-B7FFh) on the PCI bus is also supported. This configuration is non- standard, but it does allow the power management routines to support an external VGA chip. Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description |
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