CS5530A datasheet(165/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

165

Revision 1.1

General Purpose Timer 1 (GP Timer 1) Enable: Turn on GP Timer 1 and generate an SMI when the timer expires.

0 = Disable; 1 = Enable.

This idle timer’s load is multi-sourced and is reloaded any time an enabled event (F0 Index 89h[6:0]) occurs.

GP Timer 1 programming is at F0 Index 88h and 8Bh[4].

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9].

Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[0]

Index 84h

Second Level Power Management Status Mirror Register 1 (RO)

Reset Value = 00h

7:5

Reserved

Game Port SMI Status (Read Only): SMI was caused by R/W access to game port (I/O Port 200h and 201h)?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

Game Port Read SMI generation enabling is at F0 Index 83h[4].

Game Port Write SMI generation enabling is at F0 Index 53h[3].

GPIO7 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO7 pin?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[3].

GPIO5 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO5 pin?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[2].

GPIO4 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO4 pin?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[1].

GPIO3 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO3 pin?

0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[0].

Note: Properly-configured means that the GPIO pin must be enabled as a GPIO (if multiplexed pin), as an input, and to cause an SMI.

This register provides status on various power management SMI events to the SMI handler. It is called a Mirror register since an

identical register exists at F0 Index F4h. Reading this register does not clear the status, while reading its counterpart at F0 Index

F4h does clear the status.

Index 85h

Second Level Power Management Status Mirror Register 2 (RO)

Reset Value = 00h

Video Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Video Idle Timer Count Register

(F0 Index A6h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[7].

User Defined Device 3 (UDEF3) Idle Timer SMI Status (Read Only): SMI was caused by expiration of the UDEF3 Idle

Timer Count Register (F0 Index A4h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[6].

User Defined Device 2 (UDEF2) Idle Timer SMI Status (Read Only): SMI was caused by expiration of the UDEF2 Idle

Timer Count Register (F0 Index A2h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[5].

User Defined Device 1 (UDEF1) Idle Timer SMI Status (Read Only): SMI was caused by expiration of the UDEF1 Idle

Timer Count Register (F0 Index A0h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[4].

Keyboard/Mouse Idle Timer SMI Status (Read Only): SMI was caused by expiration of the Keyboard/Mouse Idle Timer

Count Register (F0 Index 9Eh)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 81h[3].

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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