CS5530A datasheet(162/259 Pages) AMD

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AMD Geode™ CS5530A Companion Device Data Book

Revision 1.1

IRQ Speedup: Any unmasked IRQ (per I/O Port 021h/0A1h) or SMI disables clock throttling (via SUSP#/SUSPA# hand-

shake) for a configurable duration when the system is power managed using CPU Suspend modulation.

0 = Disable; 1 = Enable.

The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch).

Traps: Globally enable all power management device I/O traps. 0 = Disable; 1 = Enable.

This excludes the audio I/O traps. They are enabled at F3BAR+Memory Offset 18h.

Idle Timers: Globally enable all power management device idle timers. 0 = Disable; 1 = Enable.

Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts.

This bit has no effect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h), nor on the General Purpose (UDEFx)

Timers (F0 Index 88h-8Bh). This bit must be set for the command to trigger the SUSP#/SUSPA# feature to function (see F0

Index AEh).

Power Management: Global power management. 0 = Disable; 1 = Enabled.

This bit must be set (1) immediately after POST for some power management resources to function. Until this is done, the

command to trigger the SUSP#/SUSPA# feature is disabled (see F0 Index AEh) and all SMI# trigger events listed for

F0 Index 84h-87h are disabled. A ‘0’ in this bit does NOT stop the Idle Timers if bit 1 of this register is a ‘1’, but only prevents

them from generating an SMI# interrupt. It also has no effect on the UDEF traps.

Index 81h

Power Management Enable Register 2 (R/W)

Reset Value = 00h

Video Access Idle Timer Enable: Load timer from Video Idle Timer Count Register (F0 Index A6h) and generate an SMI

when the timer expires. 0 = Disable; 1 = Enable.

If an access occurs in the video address range (sets bit 0 of the GX1 processor’s PSERIAL register) the timer is reloaded

with the programmed count.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[7].

User Defined Device 3 (UDEF3) Idle Timer Enable: Load timer from UDEF3 Idle Timer Count Register (F0 Index A4h) and

generate an SMI when the timer expires. 0 = Disable; 1 = Enable.

If an access occurs in the programmed address range the timer is reloaded with the programmed count.

UDEF3 address programming is at F0 Index C8h (base address register) and CEh (control register).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[6].

User Defined Device 2 (UDEF2) Idle Timer Enable: Load timer from UDEF2 Idle Timer Count Register (F0 Index A2h) and

generate an SMI when the timer expires. 0 = Disable; 1 = Enable.

If an access occurs in the programmed address range the timer is reloaded with the programmed count.

UDEF2 address programming is at F0 Index C4h (base address register) and CDh (control register).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[5].

User Defined Device 1 (UDEF1) Idle Timer Enable: Load timer from UDEF1 Idle Timer Count Register (F0 Index A0h) and

generate an SMI when the timer expires. 0 = Disable; 1 = Enable.

If an access occurs in the programmed address range the timer is reloaded with the programmed count.

UDEF1 address programming is at F0 Index C0h (base address register) and CCh (control register).

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[4].

Keyboard/Mouse Idle Timer Enable: Load timer from Keyboard/Mouse Idle Timer Count Register (F0 Index 9Eh) and gen-

erate an SMI when the timer expires. 0 = Disable; 1 = Enable.

If an access occurs in the address ranges (listed below) the timer is reloaded with the programmed count.

Keyboard Controller: I/O Ports 060h/064h

COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included)

COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included)

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[3].

Table 5-15. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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