SCD1283 datasheet(39/94 Pages) INTEL

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IEEE 1284-Compatible Parallel Interface — CD1283

Datasheet

5.5.8

Parallel Port Interface to the FIFO

The DMAdir bit indicates the current direction (0

= in; 1 = out) of transfers between the FIFO and

the DMA logic. Due to a recent negotiation, this can differ from the current parallel-port interface

direction. The CPU must change the direction after it receives an interrupt showing a direction

change.

The FIFOlock bit (PACR[4]) stops the DMA pipeline. This can be useful in diagnostics. FIFOlock

is also used in ECP and EPP modes to stop data transfers in the forward direction.

5.5.9

IEEE 1284-Protocol Negotiations

All IEEE 1284 protocol negotiations are initiated by the master side. The role of the CD1283 is to

accept or reject the attempted negotiation. The NER contains bits to individually enable specific

IEEE 1284 modes.

The various IEEE 1284 modes require negotiations on the parallel interface before they can be

entered. Until a successful negotiation sequence is complete, the interface remains in Compatibility

mode. These negotiations occur in two stages; both stages occur automatically after the device is

commanded to begin the negotiation procedure to a particular mode. The first stage determines if

the slave is IEEE 1284-compatible. Once determined, the interface continues the process to

determine if the mode requested is supported. The result of the requested negotiation appears in the

NSR.

For negotiations to occur, the slave must enable the E1284 bit (PCR[6]). Data transfers require that

the ETxfr bit (PCR[5]) be set; negotiations can occur without data transfer enabled.

Negotiation Status Register

After any IEEE-1284 negotiation or termination, the current protocol status can be read in the NSR.

NegOK and NegFl (bits 7:6) indicate successful and failed attempts. Invalid (bit 4) indicates that

the mode terminated from an invalid state. Termination from valid states are reported as successful

with NegOK.

A 4-bit code is displayed in the lower portion of the NSR to indicate the results of successful

negotiation. The 4-bit code in NSR also indicates the mode that the interface was in when an

invalid termination was detected, as well as a failed negotiation. Interrupts indicating a successful

negotiation into a reverse mode should prompt the CPU to load reverse data into the FIFO.

Special Command Register

The bits in the SCR cause actions on the parallel port. SetPs and ClrPs (bits 3:2) control data

movement into the CD1283 from the remote master. In Compatibility mode, this function posts

error status to the remote. Errors can only be presented to the master by the slave during the active

BUSY period. SetPs causes the CD1283 to stop transfers by asynchronously asserting the BUSY

signal. To protect against the possibility of data loss, one more byte can be strobed into the

CD1283 after BUSY goes active due to the setting of SetPs. When the error status is delivered,

ClrPs restores the parallel interface to the normal running state.

EPIrq sends an interrupt pulse in EPP mode. The RevRq bit indicates that data is available for

reverse transfer in either Compatibility or ECP mode. These operations are further described in the

relevant protocol sections.

SCD1283 Datasheet(PDF) 39 Page - Intel Corporation

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