SB710 datasheet(16/88 Pages) AMD

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AMD SB710 Databook

45215 Rev. 1.60 November 09

SB710 Power on Sequence and Timing

Power up Sequence Timing Notes

Note 1: There is no specific power sequencing requirement other than those indicated in Note

2 below. The SB710 power rails are grouped in four different voltages:

+5 V, which includes V5_VREF

II.

+3.3 V, which includes VDDQ, VDD33_18 (IDE mode)

III.

+1.2 V, which includes AVDDCK_1.2V, AVDD_SATA, PLLVDD_SATA, PCIE_PVDD,

PCIE_VDDR, CKVDD_1.2V

IV.

+1.8 V

Note 2: V5_VREF is used in the SB710 for the 5-V PCI signal tolerance. VDDQ (+3.3 V) &

VDD33_18 (3.3 V) must not exceed V5_VREF by more than 0.6 V at any time during ramp up,

steady state, or ramp down. The suggested circuit below should be used to maintain

relationship between V5_VREF and VDDQ and VDD33_18.

Figure 3-3: Circuit for Maintaining Proper Relationship between +V5_VREF and VDDQ

Note 3: The SB710 will latch the straps after rising edge of SB PWR_GOOD only once. With

debouncing of SB PWR_GOOD, the latching of strap will occur at approximately ~10ms after

the rising edge of SB PWR_GOOD.

Note 4: Typical time between A_RST# and PCIRST# is 75 ns. The measurement should be

done at 10% of both signals. Loading on the motherboard may cause the measurement at

90% be more than the spec.

Note 5: The KBRST# should be de-asserted before A_RST# (LDT_RST#) is de-asserted.

Note 6: Type II Standard and Debug straps will be latched after SB PWR_GOOD is asserted.

Type I straps are latched on resume reset rising edge. Refer to Section 4: SB710 Strap

Information

for strap timing.

Note 7: The SB710 will not monitor the ALLOW_LDTSTP signal on power up. This signal is

only used on C3 transitions.

Note 8: The PCI Clock may be stable before T11 min. under some conditions; however in all

cases, the PCI Clock is guaranteed to be stable only between T11 min and max.

Note 9: The SB710 will monitor internally the power down events and protect the internal

circuit during the power down event. This includes power down during the S3, S4, and S5

states. During an unexpected power failure or G3 state, the relationship between the 1.2 V

(VDD) and SB Power Good should be maintained to protect the internal logic of the SB710.

Note 10: The following figure shows the timing of SB PWR_GOOD de-asserted to RSMRST#

de-asserted during a power down sequence. However, this timing only applies to S0 to G3

state transition, because G3 state is where both signals are inactivated.

SB710 Datasheet(PDF) 16 Page - Advanced Micro Devices