SB710 datasheet(47/88 Pages) AMD

47 / 88 page

45215

Rev. 1.60 November 09

AMD SB710 Databook

Signal Description

Pin Name

Type

Voltage

Functional Description

RSMRST#

S5_3.3V

Resume Reset from Motherboard –

Assertion of RSMRST# resets all SB710 registers to their

default values. It also causes all reset signals originating

from the SB710 (A_RST#, PCIRST#, LDT_RST#,

AZ_RST#, AC_RST#) to be issued. RSRMT# should be

asserted when system power is being applied. Type-I straps

are captured on the rising edge of RSRMT# during its de-

assertion. RSMRST# should be de-asserted sometime after

S5 power is up, and should stay de-asserted until system

power is removed.

SYS_RESET#/GPM7#

I/O

S5_3.3V

System Reset / GPM 7

System Reset: Signal coming from the power button circuit

signaling a reset for the system. On receiving the signal, the

SB710 asserts all reset signals that originate from the

SB710 including: A_RST#, PCIRST#, LDT_RST#,

AZ_RST#, and AC_RST#; it also resets all SB710 registers

to their default values.

LAN_RST#/GPIO13

I/O

3.3 V

Early version of A_RST#; meant for resetting LAN MAC.

This signal is early to allow LAN to load its LON first

ROM_RST#/GPIO14

I/O

S5_3.3V

Early version of A_RST#, meant for resetting the system

BIOS flash

TEST0

S5_3.3V

ATE Test 0

TEST1

S5_3.3V

ATE Test 1

TEST2

S5_3.3V

ATE Test 2

7.18

Intruder Alert

Pin Name

Type

Voltage

Functional Description

Intruder_Alert#

VBAT

Intruder alert sense input

7.19

Power and Ground

Signal Name

Voltage/

Ground

ACPI

STATE

GND reference Note Description

VDD_[9:1]

1.2 V

S0-S2

VSS

Core power

VDDQ_[12:1]

3.3 V

S0-S2

VSS

3.3-V I/O Power

VDD33_18_[4:1]

3.3V

S0-S2

VSS

3.3 V power for PATA interface

S5_1.2V_[2:1]

1.2 V

S0-S5

VSS

1.2-V S5 Power

S5_3.3V_[7:1]

S5_3.3V

S0-S5

VSS

3.3-V S5 Power

AVDDCK_3.3V

3.3 V

S0-S2

AVSSCK

3.3-V power for analog PLLs

AVDDCK_1.2V

1.2 V

S0-S2

AVSSCK

1.2-V power for analog PLLs

CKVDD_1.2_[4:1]

1.2 V

S0-S2

PCIE_CK_VSS

1.2-V power for PCI-E and clock buffers

PCIE_PVDD

1.2 V

S0-S2

PCIE_VSS

A-Link Express II PLL Power

PCIE_VDDR[7:1]

1.2 V

S0-S2

PCIE_VSS

A-Link Express II Analog power

AVDD_SATA[7:1]

1.2 V

S0-S2

AVSS_SATA

SATA Analog Power

SB710 Datasheet(PDF) 47 Page - Advanced Micro Devices

SB710 Datasheet(HTML) 47 Page - Advanced Micro Devices

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