SB710 datasheet(77/88 Pages) AMD

77 / 88 page

45215

Rev. 1.60 November 09

AMD SB710 Databook

Testability

Table 14-4: Truth Table for an XOR Chain

Test Vector

number

Input Pin G

Input Pin F

Input Pin E

Input Pin D

Input Pin C

Input Pin B Output Pin A

14.2.2 Description of the SB710 XOR Chain

During XOR Chain Test Mode, most of the chip pads on the SB710 are connected together using

XOR gates as shown in Figure 14-3. The first input of the chain is connected to a logic level high

(internal connection), and all pads (listed in Table 14-5) are configured as inputs except for the

last pad in the chain, which is configured as an output. KBRST#/GEVENT1# is the start of the chain

and SERIRQ is the end of the chain. Table 14-5 lists all pads that are on the SB710 XOR chain,

as well as and their order of connection. Pads are chained together in the shown order, i.e., pad

number 1 is the first pad on the XOR chain, pad number 2 the second, and so on.

1 ( Tie high Internal to Asic)

pin 1

AD6/ROMA12

pin 2

pin 3

pin N

Frame#

XOR out

FANOUT0/ GPIO3

Figure 14-3: On-chip XOR Chain connectivity

Table 14-5: List of Pins on the SB710 XOR Chain and the Order of Connection

XOR # Pin Name

1 KBRST#/GEVENT1#

2 GA20IN/GEVENT0#

3 NB_PWRGD

4 SATA_ACT#/GPIO67

5 LDRQ1#/GNT5#/GPIO68

6 AD20

7 CBE2#

8 REQ2#

9 BMREQ#/REQ5#/GPIO65

10 REQ4#/GPIO71

11 GNT3#/GPIO72

XOR # Pin Name

12 CLKRUN#

13 REQ3#/GPIO70

14 GNT4#/GPIO73

15 INTF#/GPIO34

16 REQ1#

17 GNT1#

18 INTE#/GPIO33

19 INTH#/GPIO36

20 GNT0#

21 INTG#/GPIO35

22 AD31

SB710 Datasheet(PDF) 77 Page - Advanced Micro Devices

SB710 Datasheet(HTML) 77 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL