SB710 datasheet(53/88 Pages) AMD

53 / 88 page

45215

Rev. 1.60 November 09

AMD SB710 Databook

Functional Description

section 7.2

The host controller supports memory and IO read/write, DMA read/write, and bus master memory/IO

read/write. It supports up to two bus masters and 7 DMA channels. A bus master or DMA agent uses

LDRQ pin to assert bus master or DMA request. The host controller uses LFRAME# to indicate the start

or termination of a cycle. The following table shows a list of cycles supported by the host controller,

initiator, data flow direction, and their PCI counterparts.

Table 8-4: LPC Cycle List and Data Direction

Cycle

Size (bytes)

Initiator

Data Direction

PCI counterpart

Memory read

Host

P-2-Host

MemRead to LPC range

Memory write

Host

Host-2-P

MemWrit to LPC range

I/O read

Host

P-2-Host

IORead to LPC range

I/O write

Host

Host-2-P

IOWrit to LPC range

DMA read

1,2,4

Peripheral

Host-2-P

DMA Cntrl Setup; DMA data fetch

DMA write

1,2,4

Peripheral

P-2-Host

DMA Cntrl Setup; DMA data store

BM Memory

read

1,2,4

Peripheral

Host-2-P

DMA Cntrl Setup; DMA data fetch

BM Memory

write

1,2,4

Peripheral

P-2-Host

DMA Cntrl Setup; DMA data store

BM I/O read

1,2,4

Peripheral

Host-2-P

DMA Cntrl Setup; IO data fetch

BM I/O write

1,2,4

Peripheral

P-2-Host

DMA Cntrl Setup; IO data store

The host controller has a SERIRQ (Serial IRQ) pin, which is used by peripherals that require interrupt

support. All legacy interrupts are serialized on this pin, and then decoded by the host controller and sent

to the interrupt controller for processing. Please refer to the Serial IRQ Specification (Rev 5.4) for detailed

description on serial IRQ protocol.

SB710 Datasheet(PDF) 53 Page - Advanced Micro Devices

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