SB710 datasheet(52/88 Pages) AMD

52 / 88 page

AMD SB710 Databook

45215 Rev. 1.60 November 09

Functional Description

8.3

LPC ISA Bridge

8.3.1 LPC Interface Overview

The Low Pin Count (LPC) bus interface is a cost-efficient, low-speed interface designed to support low-

speed legacy (ISA, X-bus) devices. The LPC interface essentially eliminates the need of ISA and X-bus in

the system. A typical setup of the system with LPC interface is shown in Figure 8-2 below. Here the ISA

bus is internal to SB710 and is used for connecting to the legacy DMA logic. The LPC controller connects

to the A-Link bus on one side and the LPC and SPI bus on the other side.

Figure 8-2: A Typical LPC Bus System

Examples of LPC devices include Super I/O (floppy-disk controller, keyboard controller), BIOS, audio,

TPM, and system management controller. BIOS ROM can also be populated on the SPI interface.

SB710 can support FWH, LPC, or SPI type BIOS ROM. The ROM selection is determined by two strap

pins during RSMRST# assertion. In addition to the straps, software can change the ROM selection

through programming in the PMIO registers. SB710 SPI interface is designed to allow ROM sharing with

an external device such as an Ethernet MAC to save BOM cost. (Note: Device that shares the ROM

must follow AMD SPI ROM sharing specification).

Figure 8-3: LPC control signals diagram (TBA)

Note that the ISA interface is only used for legacy DMA operation. LPC host controller has the A-Link

interface on one side and LPC interface on the other. Some LPC signals are used for power management

in mobile systems and are therefore optional. A more detailed description of each signal is given in

SB710 Datasheet(PDF) 52 Page - Advanced Micro Devices