VR4102 datasheet(687/701 Pages) NEC

687 / 701 page

APPENDIX A DIFFERENCES BETWEEN VR4102 AND VR4101

687

A.2.3 BCU

(1) Setting of BCU Transaction

In the VR4101, the intervals of bus transactions and the number of repetitions in the enabled BCU transaction

intervals can be selectable. This function is deleted in the VR4102.

(2) Memory Access Control

16 and 32 bits are selectable as the data bus width with DBUS32 pin at reset in the VR4102 except for ISA

memory area, on the other hand, the bus width is fixed to 16 bits in the VR4101.

Though both the VR4102 and the VR4101 can select three memory types which are DRAM, masked ROM, and

Flash memory, their memory sizes and mapping method are different as summarized below.

Memory type

VR4102

VR4101

DRAM

16M-bit/64M-bit EDO x 16 bits (access time: 60 ns)

16M-bit EDO x 16 bits (access time: 60 ns)

Masked ROM

32M-bit/64M-bit ordinary or page type x 16 bits

16-bit bus mode: selected as banks0/1 or 2/3

32-bit bus mode: selected as bank0 or 1

32M-bit ordinary or page type x 16 bits

The whole ROM space is selected

Flash memory

16-bit bus mode: selected as banks0/1 or 2/3

32-bit bus mode: selected as bank0 or 1

To use the whole ROM space can be selected

(3) LCD Space

The LCD space is used only for LCD access in the VR4101, while it can be used for either LCD access or high-

speed memory access in the VR4102.

Which of LCD or high-speed memory the LCD space is used for is

selected in BCUCNT1REG register. When high-speed memory is selected, LCDCS# pin becomes active.

The access time for LCD is selectable among 2, 4, 6, and 8 TClock cycles in both the VR4102 and the VR4101.

For high-speed memory in the VR4102, the access time is selectable among 1, 2, 3, 4, 5, 6, 7, and 8 TClock

cycles. These selections of access time are set in BCUSPEEDREG register.

When transferring LCD data, inverting the data values or not is selectable in the VR4102 and is set in

BCUCNT2REG register. On the other hand, the VR4101 always inverts the values at LCD data transfer.

(4) ISA Space

In the VR4102, the bus size is dynamically controlled at every bus cycle with IOCS# and MEMCS# pins. In the

VR4101, the bus size is fixed to 8 or 16 bits and is distinguished by the accessed address space.

(5) Others

The VR4102 has bus hold function and can make ISA, LCD, and memory interfaces into bus hold state. The

VR4101 has no bus hold function, and therefore the CPU is always master state.

Bit 11..8 and bit 3..0 of PREVIDREG register indicate the revision number of the on-chip peripheral units in both

the VR4102 and the VR4101. In addition, bit 15..12 indicates the processor revision number in the VR4102,

though it is fixed to 0 in the VR4101. The remaining bits, bit 7..4, are fixed to 0 in both processors.

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