FXLS90130 datasheet(44/247 Pages) NXP

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NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

A common timer is used for all error bits in the DEVSTAT1 register. If any bit in

DEVSTAT1 is set, the timer is reset to tUVOV_RCV. When no supply errors are present, the

timer is decremented until it reaches zero. This error is cleared based on the state of the

SUP_ERR_DIS bit in the DEVLOCK_WR register as shown in Table 51.

SUP_

ERR_DIS

DSI3 and SPI operating modes

(COMMTYPE =0, 2, 3 and 4)

PSI5 operating modes

(COMMTYPE =1 and 5)

I2C operating modes

(COMMTYPE =6, 7)

No Response until the supply

monitor timer expires. The

Sensor Data Field Error Code is

transmitted for one response after

the supply monitor timer expires.

A read of the DEVSTAT1 register

clears all supply errors, using any

communication interface or on a

data transmission that includes the

error in the status field, if and only if

the timer has reached zero.

No transmissions occur if the timer

is non-zero. The error is cleared

when the timer reaches zero and

normal transmissions resume.

No transmissions occur if the timer

is non-zero. The error is cleared

when the timer reaches zero and

normal transmissions resume.

No response until the supply

monitor timer expires.

A read of the DEVSTAT1 register

clears all supply errors.

Table 51. Supply error flag (SUPPLY_ERR)

11.2.2.5 Test mode (TESTMODE)

The test mode bit is set if the device is in test mode. The TESTMODE bit can be cleared

by a test mode operation or by a power cycle.

TESTMODE

Operating mode

Test mode is not active

Test mode is active

Table 52. Test mode (TESTMODE)

11.2.2.6 Device reset (DEVRES)

The device reset bit is set following a device reset. This error is cleared by a read of the

DEVSTAT register through any communication interface or on a data transmission that

includes the error in the status field.

DEVRES

Error condition

Normal operation

Device reset occurred

Table 53. Device reset (DEVRES)

11.2.2.7 Device initialization (DEVINIT)

The device initialization bit is set following either a device reset or a change to any of the

following bits: CHx_CFG_U1[7:2] or CHx_CFG_U3[1:0]. The bit is cleared once sensor

data is valid for read through one of the device communication inter-faces (tPOR_DataValid).

FXLS9xxx0

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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