FXLS90130 datasheet(57/247 Pages) NXP

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NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

3. Optional: Execute a register read of the UF_REGION_R register and confirm the

REGION_ACTIVE[3:0] bits match the values written to the REGION_LOAD[3:0] bits in

the UF_REGION_W register.

REGION_ACTIVE[3:0]

OTP register addresses loaded into the readable

registers

Load of OTP registers is in process

The contents of the shared registers has been over-written

by the user

0010 through 1001

Not Applicable

Address Range $A0 through $AF

Address Range $B0 through $BF

Address Range $C0 through $CF

Address Range $D0 through $DF

Address Range $E0 through $EF

Address Range $F0 through $FF

Table 83. Region active bits

4. Execute a Register Read of the desired registers from the UF0, UF1, or F register

section. Complete all desired Register Reads of the selected UF Region.

5. Repeat steps 1 through 4 for the next desired UF region to read.

Notes:

• The user must take care to ensure that the desired registers are addressed. For

example, if the REGION_LOAD bits are set to 0xA and the user executes a read

of address $C2, the contents of registers $A2 are transmitted. No error detection is

included other than a read of the REGION_ACTIVE bits.

• For COMMTYPE options with multiple protocol options (COMMTYPE = '000' or '001'),

no error detection is included other than a read of the REGION_ACTIVE bits. The user

must take care to ensure that the REGION_LOAD, bits are not inadvertently changed

by an alternative protocol while executing register reads.

• In DSI3, BDM, writes to registers are inhibited. For this reason, reads of the UF0, UF1,

and F registers will only be possible for the region selected by the REGION_ACTIVE

bits at the time ENDINIT is set.

• In SPI and I2C mode, once the ENDINIT bit is set, writes to registers other than the

RESET[1:0] bits are inhibited. For this reason, reads of the UF0, UF1, and F registers

will only be possible for the region selected by the REGION_ACTIVE bits at the time

ENDINIT is set.

11.2.11 Communication type register (COMMTYPE)

The communication type register is a user programmed read/write register which

contains user-specific configuration information for communication type. This register is

included in the read/write array error detection.

This register is readable and writable in DSI3 mode, SPI mode, and I2C mode. In PSI5

Programming Mode, the value of this register must not be changed or a U_OTP Memory

occurs.

FXLS9xxx0

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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