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FXLS90130 Datasheet(PDF) 97 Page - NXP Semiconductors

Part # FXLS90130
Description  Single channel inertial sensor
PDF  247 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS90130 Datasheet(HTML) 97 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxx0
Single channel inertial sensor
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$C6
SN0
SN[7:0]
$C7
SN1
SN[15:8]
$C8
SN2
SN[23:16]
$C9
SN3
SN[31:24]
$CA
SN4
SN[39:36] = DEVICE_REV[3:0]
SN[35:32]
Table 184. Device serial number registers
Table 185 shows an example serial number decoding:
Serial number
Full serial number
Stored Data Format
SN4
SN3
SN2
SN1
SN0
Serial Number Mapping
Test ID
Lot Number
Serial Number within a lot
Example SN (Hex)
1
0
0
0
5
2
0
0
5
0
Example SN (Binary)
00
01
00
00
00
00
00
00
01
01
00
10
00
00
00
00
01
01
00
00
Example Device Rev
4'b0000 = 0x0 = 0d
Example Lot Number
4'b00 00 00 00 00 00 01 01 00 10 00 = 0x000148 = 328d
Example Serial Number
14'b00 00 00 01 01 00 00 = 0x0050 = 80d
Table 185. Example serial number decoding
11.2.43 ASIC wafer ID registers
The ASIC wafer ID registers are factory programmed OTP registers which include the
wafer number, wafer X, and Y coordinates and the wafer lot number for the device ASIC.
These registers are included in the factory programmed OTP array error detection.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming
mode when ENDINIT is not set. See Section 11.2.10 for details on the register read
process for these registers.
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$CB
ASICWFR#
ASICWFR#[7:0]
$CC
ASICWFR_X
ASICWFR_X[7:0]
$CD
ASICWFR_Y
ASICWFR_Y[7:0]
$D0
ASICWLOT_L
ASICWLOT_L[7:0]
$D1
ASICWLOT_H
ASICWLOT_H[7:0]
Table 186. ASIC wafer ID registers
11.2.44 Transducer wafer ID registers
The transducer wafer ID registers are factory programmed OTP registers which include
the wafer number, wafer X, and Y coordinates and the wafer lot number for the device
transducers. The upper 3 bits of the TRNSWFR# register include a transducer and
assembly revision counter. These registers are included in the factory programmed OTP
array error detection.
These registers are readable in DSI3 mode, SPI mode, I2C mode or PSI5 programming
mode when ENDINIT is not set. See Section 11.2.10 for details on the register read
process for these registers.
FXLS9xxx0
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
97 / 247



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