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FXLS90130 Datasheet(PDF) 75 Page - NXP Semiconductors

Part # FXLS90130
Description  Single channel inertial sensor
PDF  247 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS90130 Datasheet(HTML) 75 Page - NXP Semiconductors

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NXP Semiconductors
FXLS9xxx0
Single channel inertial sensor
DATASIZE
SPI data field size
0
12-bits
1
16-bits
Table 129. SPI data field size bit (DATASIZE)
In DSI3 mode, the DATASIZE bit is readable and writable, but has no impact on device
operation or performance.
In PSI5 mode, the DATASIZE bit is readable and writable, but has no impact on device
operation or performance.
In I2C mode, the DATASIZE bit is readable and writable, but has no impact on device
operation or performance.
11.2.20.3 SPI CRC length and seed bits (SPI_CRC_LEN[1:0], SPICRCSEED[3:0])
The SPI_CRC_LEN[1:0] bits select the CRC length for SPI mode as shown in Table 130.
The SPI CRC seed bits contain the seed used for the SPI Mode. The default SPI CRC is
an 8-bit. When the SPI_CRC_LEN[1:0] bits are set to a non-zero value using a register
write command, the SPI CRC changes as defined in the table. The new polynomial value
is enabled for both MISO and MOSI on the next SPI mode command.
The default seed (SPICRCSEED[3:0] = 0x0) is 0xFF for an 8-bit CRC. When the value
is changed to a non-zero value using a register write command, the SPI CRC seed
changes to the value programmed as shown in the table. The new seed value is enabled
for both MISO and MOSI on the next SPI mode command.
SPI_CRC_
LEN[1:0]
SPICR
CSEED
CRC polynomial
CRC seed
0
1111, 1111
0
0
Non-Zero
x8 + x5 + x3 + x2 + x + 1
1111,
SPICRCSEED[3:0]
0
1010
0
1
Non-Zero
x4 + 1
SPICRCSEED[3:0]
0
111
1
0
Non-Zero
x3 + x + 1
SPICRCSEED[2:0]
0
111
1
1
Non-Zero
x3 + x + 1
SPICRCSEED[2:0]
Table 130. SPI CRC length and seed bits (SPI_CRC_LEN[1:0], SPICRCSEED[3:0])
In PSI5 mode, the SPI CRC bits are readable and writable, but have no impact on device
operation or performance.
In DSI3 mode, the SPI CRC bits are readable and writable, but have no impact on device
operation or performance.
In I2C mode, the SPI CRC bits are readable and writable, but have no impact on device
operation or performance.
FXLS9xxx0
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2021. All rights reserved.
Product data sheet
Rev. 6 — 8 February 2021
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