FXLS90130 datasheet(73/247 Pages) NXP

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NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

• If the last command prior to a BDM command is a BRC0, a device programmed to

respond only to BRC0 commands will not respond to the first BDM command and will

then respond to every other BDM command until the next BRC command is received.

• If the last command prior to a BDM command is a BRC0, a device programmed to

respond only to BRC1 commands will respond to the first BDM command, and will then

response to every other BDM command until the next BRC command is received.

• If the last command prior to a BDM command is a BRC1, a device programmed to

respond only to BRC0 commands will respond to the first BDM command, and will then

response to every other BDM command until the next BRC command is received.

• If the last command prior to a BDM command is a BRC1, a device programmed to

respond only to BRC1 commands will not respond to the first BDM command and will

then respond to every other BDM command until the next BRC command is received.

In PSI5 mode, the BRC_RSP[1:0] bits are readable and writable, but have no impact on

device operation or performance.

In SPI and I2C mode, the BRC_RSP[1:0] bits are readable and writable, but have no

impact on device operation or performance.

11.2.19 DSI3 and PSI5 command blocking time registers (PDCM_CMD_B_x)

The DSI3 and PSI5 command blocking registers are user programmed read/write

registers which contain user-specific con-figuration information for DSI3 mode and PSI5

mode. These registers are included in the read/write array error detection.

These registers are readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

programming mode.

Location

Bit

Address

$38

PDCM_

CMD_B_L

PDCM_CMD_B[7:0]

$39

PDCM_

CMD_B_H

RESERVED

PDCM_CMD_B[12:8]

Unprogrammed OTP Value

Table 124. DSI3 and PSI5 command blocking time registers (PDCM_CMD_B_x)

In DSI3 mode, the DSI3 periodic data collection mode command blocking time bits

set the periodic data collection mode command blocking time in 1.0 µs increments,

with zero as the default value of 450 µs. For proper communication, the command

blocking time must exceed the completion of the last source response transmission. See

Section 12.1.1 for details regarding the command receiver and command blocking.

Care must be taken to prevent from programming command blocking times which

prevent proper command decoding in the system and to ensure proper sampling of the

VHIGH voltage. As shown in Section 12.1.1, Figure 63, the VHIGH voltage is initially

captured at the end of the command blocking time and then filtered. The user must

ensure that the command blocking end time is set for a time when no command or

response transmissions are occurring to provide the most stable BUS_I voltage.

PDCM_CMD_B[12:0] Sync pulse blocking time

450 µs

Non-Zero

Sync Pulse Blocking Time = PDCM_CMD_B x 1 µs

Table 125. DSI3 mode: Command blocking time bits

FXLS9xxx0

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Product data sheet

Rev. 6 — 8 February 2021

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