FXLS90130 datasheet(69/247 Pages) NXP

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NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

11.2.17.1 Sync pulse pull-down enable bit (SYNC_PD)

In PSI5 mode, the sync pulse pull-down enable bit selects if the Sync pulse pull-down

is enabled once a sync pulse is detected. See Section 11.2.18.1 for more information

regarding the sync pulse pulldown.

SYNC_PD

Sync pulse pull-down

Disabled

Enabled for all PSI5 operating modes

Table 113. Sync pulse pull-down enable bit (SYNC_PD)

In DSI3 mode, the SYNC_PD bit is readable and writable, but has no impact on device

operation or performance.

In SPI and I2C mode, the SYNC_PD bit is readable and writable, but has no impact on

device operation or performance.

11.2.17.2 PSI5 daisy chain selection bit (DAISY_CHAIN)

In PSI5 mode, the transmission mode selection bits select the PSI5 transmission mode

as shown in Table 114.

DAISY_

CHAIN

Operating mode

Response (PDCM_

RSTST0)

Reference

Normal Mode (Asynchronous or Parallel,

Synchronous)

SNSDATA0

Section 13.5

Daisy Chain Mode

SNSDATA0

Section 13.7

Table 114. PSI5 daisy chain selection bit (DAISY_CHAIN)

In DSI3 mode, the DAISY_CHAIN bit is readable and writable, but has no impact on

device operation or performance.

In SPI and I2C mode, the DAISY_CHAIN bit is readable and writable, but has no impact

on device operation or performance.

11.2.17.3 PSI5 low response current selection bit (PSI5_ILOW)

In PSI5 mode, the PSI5 low response current selection bit selects the low PSI5 response

current specified in Section 10.4 as shown in Table 115.

PSI5_ILOW

PSI5 response current

Normal Response Current

Low Response Current

Table 115. PSI5 low response current selection bit (PSI5_ILOW)

In DSI3 mode, the PSI5_ILOW bit is readable and writable, but has no impact on device

operation or performance.

In SPI and I2C mode, the PSI5_ILOW bit is readable and writable, but has no impact on

device operation or performance.

FXLS9xxx0

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Product data sheet

Rev. 6 — 8 February 2021

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