FXLS90130 datasheet(74/247 Pages) NXP

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NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

In PSI5 mode, the command blocking time bits set the PSI5 sync pulse blocking time in

1.0 µs increments, with zero as the default value of 450 µs. See Section 13.2.1 for details

regarding the PSI5 sync pulse receiver and command blocking.

Care must be taken to prevent from programming command blocking times which

prevent proper sync pulse decoding in the system and to ensure proper sampling of the

PSI5 voltage.

PDCM_CMD_B[12:0] Sync pulse blocking time

0, 1, 2, 3, 4, 5, 6, 7, 8, 9 450 µs

10 - 8191

Sync Pulse Blocking Time = PDCM_CMD_B x 1 µs

Table 126. PSI5 mode: Command blocking time bits

In SPI and I2C mode, the PDCM_CMD_B bits are readable and writable, but have no

impact on device operation or performance.

11.2.20 SPI configuration control register

In SPI mode, the SPI configuration control register is a user programmed read/write

included in the read/write array error detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

programming mode.

Location

Bit

Address

$3D

SPI_CFG

SPI_STATUS

DATASIZE

SPI_CRC_LEN[1:0]

SPICRCSEED[3:0]

Unprogrammed OTP Value

Table 127. SPI configuration control register

11.2.20.1 SPI status reporting selection bit (SPI_STATUS)

The SPI status reporting bit controls the reporting of the SPI basic status as shown in

Table 128. See Section 14.5.

SPI_STATUS

SPI basic status reporting

As documented in Section 14.5.1

As documented in Section 14.5.2

Table 128. SPI status reporting selection bit (SPI_STATUS)

In DSI3 mode, the SPI_STATUS bit is readable and writable, but has no impact on device

operation or performance.

In PSI5 mode, the SPI_STATUS bit is readable and writable, but has no impact on device

operation or performance.

In I2C mode, the SPI_STATUS bit is readable and writable, but has no impact on device

operation or performance.

11.2.20.2 SPI data field size bit (DATASIZE)

The SPI data field size bit controls the size of the SPI data field as shown in Table 129.

See Section 11.6.4.9.

FXLS9xxx0

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Product data sheet

Rev. 6 — 8 February 2021

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