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FXLS90130 Datasheet(PDF) 47 Page - NXP Semiconductors |
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FXLS90130 Datasheet(HTML) 47 Page - NXP Semiconductors |
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47 / 247 page ![]() NXP Semiconductors FXLS9xxx0 Single channel inertial sensor CONT_ERR Error condition 0 No error detected 1 Error detected in the continuity of the monitor circuit Table 61. Continuity monitor error (CONT_ERR) 11.2.2.15 NXP OTP array error (F_OTP_ERR) The factory OTP array error bit is set if a fault is detected in the factory OTP array. This error is cleared by a device reset. See Section 11.2.15.2 for details on a method to disable the automatic clearing of this error in PSI5 mode. F_OTP_ERR Error condition 0 No error detected 1 Error Detected in the Factory OTP Array Table 62. NXP OTP array error (F_OTP_ERR) 11.2.2.16 User OTP array error (U_OTP_ERR) The user OTP array error bit is set if a fault is detected in the user OTP array. This error is cleared by a device reset. See Section 11.2.15.2 for details on a method to disable the automatic clearing of this error in PSI5 mode. U_OTP_ERR Error condition 0 No error detected 1 Error Detected in the User OTP Array Table 63. User OTP array error (U_OTP_ERR) 11.2.2.17 User read/write array error (U_RW_ERR) When ENDINIT is set, an error detection is enabled for all user writable registers. The error detection code is continuously calculated on the user writable registers and verified against a previously calculated error detection code. If a mismatch is detected in the error detection, the U_RW_ERR bit is set. This error is cleared by a read of the DEVSTAT2 register through any communication interface or on a data transmission that includes the error in the status field. See Section 11.2.15.2 for details on a method to disable the automatic clearing of this error in PSI5 mode. U_RW_ERR Error condition 0 No error detected 1 Error Detected in the User Read/Write Array Table 64. User read/write array error (U_RW_ERR) 11.2.2.18 User OTP write in process status bit (U_W_ACTIVE) The user OTP write in process status bit is set if a user initiated write to OTP is currently in process. The U_W_ACTIVE bit is automatically cleared once the write to OTP is complete. FXLS9xxx0 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved. Product data sheet Rev. 6 — 8 February 2021 47 / 247 |
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