FXLS90130 datasheet(46/247 Pages) NXP

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NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

11.2.2.11 Internal analog regulator voltage out of range error (INTREGA_ERR)

The internal analog regulator voltage out of range error bit is set if the internal analog

regulator voltage falls outside expected limits. A common timer is used for all error bits

in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV.

This bit is cleared based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR

INTREGA_ERR

Error condition

No error detected

Internal Analog Regulator Voltage Out of Range

Table 58. Internal analog regulator voltage out of range error (INTREGA_ERR)

11.2.2.12 Internal digital regulator voltage out of range error (INTREG_ERR)

The internal digital regulator voltage out of range error bit is set if the internal digital

regulator voltage falls outside expected limits. A common timer is used for all error bits

in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV.

This bit is cleared based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR

INTREG_ERR

Error condition

No error detected

Internal Digital Regulator Voltage Out of Range

Table 59. Internal digital regulator voltage out of range error (INTREG_ERR)

11.2.2.13 Internal OTP regulator voltage out of range error (INTREGF_ERR)

The internal OTP regulator voltage out of range error bit is set if the internal OTP

regulator voltage falls outside expected limits. A common timer is used for all error bits

in the DEVSTAT1 register. If any supply error is present, the timer is reset to tUVOV_RCV.

This bit is cleared based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR

INTREGF_ERR

Error condition

No error detected

Internal OTP Regulator Voltage Out of Range

Table 60. Internal OTP regulator voltage out of range error (INTREGF_ERR)

11.2.2.14 Continuity monitor error (CONT_ERR)

The continuity monitor passes a low current through a connection around the perimeter

of the device and monitors the continuity of the connection. The error bit is set if a

discontinuity is detected in the connection. A common timer is used for all error bits in the

DEVSTAT1 register. If the CONT_ERR bit is set, the timer is reset to tUVOV_RCV. This bit

is cleared based on the state of the SUP_ERR_DIS bit in the DEVLOCK_WR register as

shown in Section 11.2.2.4.

FXLS9xxx0

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Product data sheet

Rev. 6 — 8 February 2021

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