FXLS90130 datasheet(85/247 Pages) NXP

85 / 247 page

NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

ST_

CTRL[3]

ST_

CTRL[2]

ST_

CTRL[1]

ST_

CTRL[0]

Function

16-bit

SNSDATAx

value

signed

Effect on

ST_

INCMPLT

bit in Chx_

STAT

Effect on

ST_ACTIVE

bit in Chx_

STAT

Clear on

Activation

Set When

Active

0x0000

Clear on

Activation

Set When

Active

0xAAAA

Clear on

Activation

Set When

Active

0x5555

Clear on

Activation

Set When

Active

DSP write to registers inhibited.

0xFFFF

Clear on

Activation

Set When

Active

Positive Analog Self-test - Low

Clear on

Activation

Set When

Active

Negative Analog Self-test - Low

Clear on

Activation

Set When

Active

Positive Analog Self-test - High

Clear on

Activation

Set When

Active

Negative Analog Self-test - High

Sensor Data

Clear on

Activation

Set When

Active

Clear on

Activation

Set When

Active

Clear on

Activation

Set When

Active

Clear on

Activation

Set When

Active

Digital Self-test

Reference

Section 10.8

Clear on

Activation

Set When

Active

Table 151. Self-test control bits (ST_CTRL[3:0])...continued

11.2.27.2 Offset cancellation test limit bits (OC_LIMIT[2:0])

The offset cancellation test limit bits set the offset limits for the offset test at the end of

the PSI5 self-test documented in Section 11.6.2.5. The test limits are set as shown in

Table 152.

OC_LIMIT[2:0]

Post PSI5 self-test offset limits

0x0

The post PSI5 self-test offset test is disabled.

0x1

± 2 LSB, 10-bit

0x2

± 4 LSB, 10-bit

0x3

± 6 LSB, 10-bit

0x4

± 8 LSB, 10-bit

0x5

± 10 LSB, 10-bit

Table 152. Offset cancellation test limit bits (OC_LIMIT[2:0])

FXLS9xxx0

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Product data sheet

Rev. 6 — 8 February 2021

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