FXLS90130 datasheet(64/247 Pages) NXP

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NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

CK_CAL_EN CK_CAL_RST Oscillator training

The oscillator value is maintained at the last trained value prior

to clearing the CK_CAL_RST bit.

The oscillator value is reset to the untrained value with a

tolerance specified in Section 10.20.

Oscillator is trained as specified in Section 11.5.1

Table 98. Clock calibration enable (CK_CAL_EN)

11.2.15 Chip time and bit time register (CHIPTIME)

The chip time and bit time register is a user programmed read/write register which

contains user-specific configuration information. This register is included in the read/write

array error detection.

This register is readable and writable in DSI3 mode, SPI mode, I2C mode or PSI5

Programming Mode.

Location

Bit

Address

$23

CHIPTIME

ST_RPT[1:0]

PSI5_

ERRLATCH

SS_EN

CHIPTIME[3:0]

Unprogrammed OTP Value

FXLS93xxx

Unprogrammed

Default PSI5 Mode

Table 99. Chip time and bit time register (CHIPTIME)

11.2.15.1 PSI5 self-test repetition bits (ST_RPT[1:0])

In PSI5 mode, the PSI5 self-test repetition bits set the maximum number of PSI5 self-test

repetitions that the device will run before setting the ST_ERROR bit. See Section 6.6.2.5

for details regarding the PSI5 startup self-test.

ST_RPT[1]

ST_RPT[0]

Maximum PSI5 self-test repetitions

Table 100. PSI5 self-test repetition bits (ST_RPT[1:0])

11.2.15.2 PSI5 error latching enable bit (PSI5_ERRLATCH)

In PSI5 mode, the PSI5 error latching enable bit allows for users to disable the automatic

error clearing mechanism for internal faults. When this bit is set, internal errors are

latched until reset. See Section 13.8.4 and Section 13.8.5 for details regarding internal

error handling.

FXLS9xxx0

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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