FXLS90130 datasheet(63/247 Pages) NXP

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NXP Semiconductors

FXLS9xxx0

Single channel inertial sensor

COMMTYPE

OSCTRAIN_SEL

Protocol to use for oscillator training

DSI3

SPI

PSI5

SPI

DSI3

SPI

PSI5

I2C

Table 96. Oscillator training protocol selection bit (OSCTRAIN_SEL)

11.2.14.3 Clock calibration value reset (CK_CAL_RST)

The clock calibration reset bit controls the state of the oscillator training when the

CK_CAL_EN bit is cleared as described in the table in Section 11.2.14.5. See

Section 11.5.1 for details regarding oscillator training.

11.2.14.4 Command and response mode period (CRM_PER[1:0])

In DSI3 mode, the command and response mode period bits set the period for command

and response mode commands in increments of the periodic data collection mode period

(PDCM_PER). This value is only necessary for DSI3 oscillator training and is only used

if the CK_CAL_EN bit is set in the TIMING_CFG register. command and response mode

commands will be decoded and responded to regardless of the value of this register

as long as the general command and response mode timing parameters specified in

Section 10.11 are met. See Section 11.5.1 for details regarding oscillator training.

In SPI and I2C mode, the CRM_PER[1:0] bits are readable and writable, but have no

impact on device operation or performance.

In PSI5 mode, the CRM_PER[1:0] bits are readable and writable, but have no impact on

device operation or performance.

CRM_PER[1]

CRM_PER[0]

Command and response mode period

(Multiples of the periodic data collection mode period)

Table 97. Command and response mode period (CRM_PER[1:0])

11.2.14.5 Clock calibration enable (CK_CAL_EN)

The clock calibration enable bit enables oscillator training over the DSI3, PSI5, SPI, or

I2C communication interface. See Section 11.5.1 for details regarding oscillator training.

FXLS9xxx0

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 8 February 2021

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